Date: Thu, 12 Sep 1996 02:12:56 -0600 From: Steve Passe <smp@csn.net> To: Peter Wemm <peter@spinner.dialix.com> Cc: rv@groa.uct.ac.za (Russell Vincent), freebsd-smp@freebsd.org Subject: Re: Intel XXpress - some SMP benchmarks Message-ID: <199609120812.CAA15528@clem.systemsix.com> In-Reply-To: Your message of "Thu, 12 Sep 1996 14:40:41 %2B0800." <199609120640.OAA02113@spinner.DIALix.COM>
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Hi,
> Hmm, something seems to have gone wrong, my second CPU isn't found with
> this patch present, so I'll see if I can see what went wrong..
I stripped out some debug while making the report, perhaps I broke something.
I am currently rebuilding the world, I will apply the reported patch and
verify whether it works when I've finished supping/building SMP.
For my information, what motherboard are you using?
---
> Hint: ALL the APIC ID registers are read/write.
>
> Can you see it yet? :-)
we tried that on the XXPRESS and (Russel, please confirm this) an instant reset
of the hardware. My mail notes show:
----------------------------- mail from Russel ------------------------------
> one last experiment. the book says that you can write the local apic id.
> so the locore.s I just sent does that. you need to turn OFF "#define XXPRESS"
> in i386/include/smpasm.h (and anywhere else you have set it). specifically it
> causes the 2nd CPU to change its apic ID from 2 to 1 during its early
> bootup code, so we still want CPUNUMBER=0x02000000 for the 1st CPU INIT IPI
> code, but after that everything should be in the context of 2nd CPU apic ID=1.
I removed my 'options XXPRESS' line and did a 'config SMP' and
re-compiled with the new locore.s. Now the machine reboots as
soon as I do the sysctl.
------------------------------- end mail notes --------------------------------
We could have had another problem at this point so further experimentation
wouldn't hurt.
---
>Apart from the existance of the XXPRESS board, the nice easy solution is
>to have the boot cpu assign it's ID to zero, and send a broadcast STARTUP
>IPI and have the application cpu's fight for a lock, and assign themselves
>sequentially increasing ID's, and assign the IO apic's ID to the end of
>the list.
my databook says:
110( Startup) This delivery mode is used as a special message
between two processors ...
ie, are you sure you can do broadcast 'Startup IPIs'?
as an alternative I would suggest starting to use the MP table:
#define MAX_CPU 16
int SMPIDMap[ MAX_CPU ];
int nextCpu( void** fps ) { /* finds next cpu record in MP table @ fps */ }
infoFromMPTable()
{
int mp_ncpus = 0;
void* fps = mpfps;
while ( nextCpu( &fps ) )
{
id = CpuId( fps )
SMPIDMap[ id ] = mp_ncpus++;
}
}
cpunumber()
{
return SMPIDMap[ GETCPUID() ];
}
I've already written code that dumps the entire table, I could produce routines
like nextCpu() in quick order.
another issue to consider is that when you write the APIC ID register you also
write its ARB (arbitration) register. Since I haven't yet deciphered
the arbitration stuff I can't say whether this is an issue...
---
>One thing I'm not clear about from the IO apic docs yet is whether there
>are 15 cpu's and 15 IO apic's, or whether there's a limit of 15 devices on
>the APIC bus.
my belief is that it is a total of 15.
the true 82489 has an 8-bit register, but the IO APIC in 586/686
has a 4-bit field as does the 82379AB and 82093AA.
On my mb the IO APIC is numbered 2, while the XXPRESS numbers it 14.
>BTW, those .pdf docs you pointed out have done the trick and describe the
.IO apic (version 0x11 at least :-) completely, although it is scattered
>around different doc files a bit..
did you get the book info I mailed earlier today about finding the true
datasheet for the 82489?
>As I understand it, the 82371SB PIIX3 chip has an IO apic address decoder,
>but no apic. The IOAPIC chip (82093AA) is an optional extra part of the
>430HX suite and would only be present on the multi-processor boards. I'm
good eye, I didn't see this detail on my first scan of that doc.
--
Steve Passe | powered by
smp@csn.net | FreeBSD
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