Date: Mon, 16 Sep 1996 22:28:14 -0700 From: "Michael L. VanLoon -- HeadCandy.com" <michaelv@MindBender.serv.net> To: Michael Smith <msmith@atrad.adelaide.edu.au> Cc: hardware@freebsd.org Subject: Re: RAM timings for Triton chipsets? Message-ID: <199609170528.WAA22129@MindBender.serv.net> In-Reply-To: Your message of Tue, 17 Sep 96 14:55:24 %2B0930. <199609170525.OAA29451@genesis.atrad.adelaide.edu.au>
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>Michael L. VanLoon -- HeadCandy.com stands accused of saying:
>> x2222 and x4444 mean how many cycles it takes to access memory for
>> each cycle of a burst read or write. The x means that the first
>> access is longer (typically something like 6 cycles). After the first
>> access, it can burst at a word for every 2 bus cycles (or as the case
>> is now, for ever 4 bus cycles).
>Hmm. It certainly isn't behaving 'much slower'... What sort of
>'much' would you expect from that sort of change?
Small things that fit nicely in your cache probably won't be noticably
slower. Stuff that will are big processes that touch a lot of memory.
Like piggy GCC doing a large build.
Try doing a clean kernel compile with the settings each way and see
what you get.
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Michael L. VanLoon michaelv@MindBender.serv.net
--< Free your mind and your machine -- NetBSD free un*x >--
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NetBSD ports in progress: PICA, others...
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