Date: Wed, 23 Apr 2008 13:03:52 +0900 From: "Naoki Hamada" <nao@tom-yam.or.jp> To: freebsd-mips@freebsd.org Subject: minor fix for tlb manipulations Message-ID: <2da2ec620804222103r7e90af37j2d36b0f0bc049abb@mail.gmail.com>
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[-- Attachment #1 --] Hi, I found a slight problem in tlb.S which tries to manipulate no-existing tlbs. The argument of Mips_TLBFlush() and mips_TBIAP() is the number of tlbs to deal with, but both functions process the same number of tlb pairs, so twice the number of actual tlbs. TLBWI entry of "MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set" states that "The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of TLB entries in the processor." It seems to do no harm to my system, but your mileage may vary. Included patches remedy this problem, but strictly speaking, it does not properly works if the argument is an odd number, I hardly imagine in which situation it occurs. Naoki Hamada nao@tom-yam.or.jp [-- Attachment #2 --] diff -ur src.orig/sys/mips/mips/tlb.S src/sys/mips/mips/tlb.S --- src.orig/sys/mips/mips/tlb.S 2008-03-31 15:55:56.000000000 +0900 +++ src/sys/mips/mips/tlb.S 2008-04-22 09:25:13.000000000 +0900 @@ -239,6 +239,7 @@ _MTC0 zero, COP_0_TLB_LO0 # Zero out low entry0. _MTC0 zero, COP_0_TLB_LO1 # Zero out low entry1. mtc0 zero, COP_0_TLB_PG_MASK # Zero out mask entry. + srl a0, a0, 1 # assume even number /* * Align the starting value (t1) and the upper bound (a0). */ @@ -471,7 +472,7 @@ mtc0 zero, COP_0_STATUS_REG # disable interrupts _MFC0 t4, COP_0_TLB_HI # Get current PID - move t2, a0 + srl t2, a0, 1 # assume even number mfc0 t1, COP_0_TLB_WIRED li v0, MIPS_KSEG0_START + 0x0fff0000 # invalid address mfc0 t3, COP_0_TLB_PG_MASK # save current pgMaskhome | help
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