Date: Tue, 27 Sep 2011 18:56:13 +0300 From: Alexander Motin <mav@FreeBSD.org> To: Adrian Chadd <adrian@freebsd.org> Cc: freebsd-current@freebsd.org Subject: Re: ath / 802.11n performance issues and timer code Message-ID: <4E81F21D.7000209@FreeBSD.org> In-Reply-To: <4E81E4A1.3070301@FreeBSD.org> References: <CAJ-VmomZyDJV62yCQOvG=UB6H4wfz9=3_cWzEL7vWAA14TCyYA@mail.gmail.com> <201109261053.30410.jhb@freebsd.org> <CAJ-VmomyMQpcpHo4ve-_O67_8VVJW-YRqWeb-7exSxzV5rz_pA@mail.gmail.com> <201109261305.57602.jhb@freebsd.org> <CAJ-Vmo=ZBwBu6Mk=XdY1p18s5=kQvmC3qZc1JzPtpppGBs4Z=Q@mail.gmail.com> <CAJ-Vmong0dJN=t=Qq4%2BaLyBGxEKAKBd8oX4y9P0goux%2BZAc3yA@mail.gmail.com> <CAJ-VmonbAgsNjdCstd_Ap6JBqowD1NX0J5rQ=t9ideaiXTXd%2BA@mail.gmail.com> <4E81E4A1.3070301@FreeBSD.org>
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Alexander Motin wrote:
> Adrian Chadd wrote:
>> .. erm, sys/mips/mips/machdep.c:
>>
>> /*
>> * call platform specific code to halt (until next interrupt) for the idle loop
>> */
>> void
>> cpu_idle(int busy)
>> {
>> KASSERT((mips_rd_status() & MIPS_SR_INT_IE) != 0,
>> ("interrupts disabled in idle process."));
>> KASSERT((mips_rd_status() & MIPS_INT_MASK) != 0,
>> ("all interrupts masked in idle process."));
>>
>> if (!busy) {
>> critical_enter();
>> cpu_idleclock();
>> }
>> __asm __volatile ("wait");
>> if (!busy) {
>> cpu_activeclock();
>> critical_exit();
>> }
>> }
>>
>> .. does that look right?
>
> Yes it does. x86 does the same, but with more details. The general idea
> of the critical section is to block context switch out of idle thread
> until missed time events will be handled inside cpu_activeclock().
I was wrong. That's not good. I have no idea about mips wait instruction
semantics, related to disabling interrupts. In x86 semantics proper
solution is:
disable_intr();
if (sched_runnable())
enable_intr();
else
__asm __volatile("sti; hlt");
It makes interrupts enabled atomically with entering sleep state, that
closes race window and prevents entering into sleep after receiving
interrupt.
--
Alexander Motin
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