Date: Thu, 21 Jun 2012 12:47:38 +0300 From: Alexander Motin <mav@FreeBSD.org> To: freebsd-arm@FreeBSD.org Subject: Cache write-back issue on Marvell SoC (SheevaPlug) Message-ID: <4FE2EDBA.1030505@FreeBSD.org>
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Hi.
Trying to localize regular data corruption during writes (reads seems
not affected) to SATA disk on SheevaPlug box I've found out that it is
probably result of cache coherency issue. Reading data back shows that
each time exactly 32 sequential aligned data bytes are corrupted. That,
if I understand correctly, matches single cache line size/offset.
I've found out that such dirty hack with flushing all D-cache after
doing normal bus_dmamap_sync() fixes the situation:
--- mvs.c (revision 237359)
+++ mvs.c (working copy)
@@ -1307,6 +1312,10 @@ mvs_dmasetprd(void *arg, bus_dma_segment_t *segs,
bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
+#if defined(__arm__)
+ if (slot->ccb->ccb_h.flags & CAM_DIR_OUT)
+ cpu_dcache_wbinv_all();
+#endif
if (ch->basic_dma)
mvs_legacy_execute_transaction(slot);
else
Unluckily I have no idea in arm assembler and cache control interfaces.
Could somebody recheck existing D-cache range write-back code, because
there seems to be a problem?
--
Alexander Motin
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