Date: Thu, 1 Jul 2010 04:10:05 +0530 From: "Jayachandran C." <c.jayachandran@gmail.com> To: Luiz Otavio O Souza <lists.br@gmail.com> Cc: freebsd-mips@freebsd.org Subject: Re: Merging 64 bit changes to -HEAD Message-ID: <AANLkTimgyYggdDYchEfb3yskmA0PsttjVzkOSMaWFsjH@mail.gmail.com> In-Reply-To: <C1BD2512-8A48-4AB2-B9CA-C46DDCBE5256@gmail.com> References: <AANLkTik8jFkB7FTIIhyjalkfv1c0yXqse57Jzz527uf_@mail.gmail.com> <897604F6-95C4-49A8-B11F-277A74C8DBAE@gmail.com> <AANLkTilfW_zOFKuIa0gJ3ahTo-vGC1VNk99a1H24uFRq@mail.gmail.com> <AANLkTil78NFxH016C7MntD8L3d4rFlCudJ0Lv22L0KCb@mail.gmail.com> <3C0AEF9B-AE0C-4459-A4E1-2C8C30C10FD6@gmail.com> <AANLkTint7Hyf79EH29OLsIfreQRd7dQMdvX9wRq4v_yG@mail.gmail.com> <C6D73C96-3640-4502-A9D7-B3597E37E80A@gmail.com> <AANLkTilQIqF4FCfgLdVcKdcsAUVjCmr89Lu0TEXUFdYN@mail.gmail.com> <25B9A19D-0A6B-4731-8FB1-A2C6722F0E9C@gmail.com> <AANLkTim_9-G6ZuA0vkpLeG4n4GVBpBlxhGBy_7eQoIM4@mail.gmail.com> <C1BD2512-8A48-4AB2-B9CA-C46DDCBE5256@gmail.com>
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[-- Attachment #1 --] On Wed, Jun 30, 2010 at 10:38 PM, Luiz Otavio O Souza <lists.br@gmail.com> wrote: > On Jun 30, 2010, at 9:57 AM, Jayachandran C. wrote: > >> On Tue, Jun 29, 2010 at 10:32 PM, Luiz Otavio O Souza >> <lists.br@gmail.com> wrote: >>> >>> On Jun 29, 2010, at 8:02 AM, Jayachandran C. wrote: >>> >>>> On Tue, Jun 29, 2010 at 2:28 AM, Luiz Otavio O Souza <lists.br@gmail.com> wrote: >>>>>> Thanks for the the update. Looks like pmap_map for kernel is failing, >>>>>> may be the new tlb_update code causes this. Can you apply the >>>>>> attached patch and see if the problem still persists, it replaces the >>>>>> new tlb_update code with the older version. >>>>>> >>>>>> Obviously not a fix, but if we can narrow it down to this function, >>>>>> fixing will be easier. >>>>>> >>>>>> JC. >>>>>> <try.diff> >>>>> >>>>> JC, >>>>> >>>>> This fix the problem ! Thanks ! Now, at least, you know where to look :) >>>> >>>> The new tlb_update does not seem to update the tlb entry if the tlbp >>>> fails. Here's a patch that should make the new function behave like >>>> the older one. The patch is in attached file 'tlb-update.diff'. >>>> >>>> If that does not work, I'm not sure what the issue is. You could also >>>> try try the nop-change.diff attached. It tries to switch the ssnop >>>> used for delay in the new code with 'nop' which was used by the old >>>> code. >>>> >>>> Thanks, >>>> JC. >>>> <tlb-update.diff><nop-change.diff> >>> >>> JC, >>> >>> The nop-change seems to have no effect at all and with the tlb-update patch the kernel apparently crash at bzero(), here is the dmesg with TRAP_DEBUG enabled: >>> >>> http://mips.pastebin.com/jydPvJ20 >>> >>> So hopefully you are on the right track and this may be something obvious to you. >> >> Not yet :) I really hoped the earlier change would fix it. The number >> of nop does not seem to be the issue as it is higher in the C code >> than the assembly. >> >> Can you try the attached patch (try.diff) - this re-implements the >> assembly code functionality almost in the same way in C. This really >> should work, given that the patch which made it assembly worked... >> >> If that works can you see if the second attached patch works, this >> fixes a potential problem (ie, we should be masking 13bits for TLBHI). >> >> Both patches should apply directly to SVN (not dependent on each >> other, or on previous patches) >> >> Thanks again, >> JC. >> <try.diff><pte.h-fix.diff> > > > JC, > > The try.diff works with or without the pte.h change (at least for a simple boot) and the pte.h change does nothing without the try.diff. I've attached the final(final.diff) version I want to check-in, can you please quickly test it? If that does not work, can you tell me if the attached alt1.diff or alt2.diff works? The try.diff had three changes: handle case of index>0, remove pagemask operation, restore full entryhi instead of asid. So if the first does not work, this will help narrow down the rest of the cases. Hopefully this is the last iteration :) JC. [-- Attachment #2 --] Index: sys/mips/include/pte.h =================================================================== --- sys/mips/include/pte.h (revision 209521) +++ sys/mips/include/pte.h (working copy) @@ -73,7 +73,8 @@ * Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page. */ #define TLBHI_ASID_MASK (0xff) -#define TLBHI_ENTRY(va, asid) (((va) & ~PAGE_MASK) | ((asid) & TLBHI_ASID_MASK)) +#define TLBHI_PAGE_MASK (2 * PAGE_SIZE - 1) +#define TLBHI_ENTRY(va, asid) (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK)) #ifndef _LOCORE typedef uint32_t pt_entry_t; Index: sys/mips/mips/tlb.c =================================================================== --- sys/mips/mips/tlb.c (revision 209521) +++ sys/mips/mips/tlb.c (working copy) @@ -217,30 +217,41 @@ void tlb_update(struct pmap *pmap, vm_offset_t va, pt_entry_t pte) { - register_t mask, asid; + pt_entry_t other; + register_t mask, asid, hi; register_t s; - int i; + int i, even; - va &= ~PAGE_MASK; + s = intr_disable(); + even = (va & PAGE_SIZE) == 0; pte &= ~TLBLO_SWBITS_MASK; - - s = intr_disable(); + hi = TLBHI_ENTRY(va, pmap_asid(pmap)); mask = mips_rd_pagemask(); asid = mips_rd_entryhi() & TLBHI_ASID_MASK; - - mips_wr_pagemask(0); - mips_wr_entryhi(TLBHI_ENTRY(va, pmap_asid(pmap))); + mips_wr_entryhi(hi); tlb_probe(); i = mips_rd_index(); if (i >= 0) { tlb_read(); - if ((va & PAGE_SIZE) == 0) { + if (even) { mips_wr_entrylo0(pte); } else { mips_wr_entrylo1(pte); } tlb_write_indexed(); + } else { + other = pte & PTE_G; + mips_wr_pagemask(0); + mips_wr_entryhi(hi); + if (even) { + mips_wr_entrylo0(pte); + mips_wr_entrylo1(other); + } else { + mips_wr_entrylo0(other); + mips_wr_entrylo1(pte); + } + tlb_write_random(); } mips_wr_entryhi(asid); [-- Attachment #3 --] Index: sys/mips/include/pte.h =================================================================== --- sys/mips/include/pte.h (revision 209521) +++ sys/mips/include/pte.h (working copy) @@ -73,7 +73,8 @@ * Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page. */ #define TLBHI_ASID_MASK (0xff) -#define TLBHI_ENTRY(va, asid) (((va) & ~PAGE_MASK) | ((asid) & TLBHI_ASID_MASK)) +#define TLBHI_PAGE_MASK (2 * PAGE_SIZE - 1) +#define TLBHI_ENTRY(va, asid) (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK)) #ifndef _LOCORE typedef uint32_t pt_entry_t; Index: sys/mips/mips/tlb.c =================================================================== --- sys/mips/mips/tlb.c (revision 209521) +++ sys/mips/mips/tlb.c (working copy) @@ -217,30 +217,41 @@ void tlb_update(struct pmap *pmap, vm_offset_t va, pt_entry_t pte) { - register_t mask, asid; + pt_entry_t other; + register_t mask, asid, hi; register_t s; - int i; + int i, even; - va &= ~PAGE_MASK; + s = intr_disable(); + even = (va & PAGE_SIZE) == 0; pte &= ~TLBLO_SWBITS_MASK; - - s = intr_disable(); + hi = TLBHI_ENTRY(va, pmap_asid(pmap)); mask = mips_rd_pagemask(); - asid = mips_rd_entryhi() & TLBHI_ASID_MASK; - - mips_wr_pagemask(0); - mips_wr_entryhi(TLBHI_ENTRY(va, pmap_asid(pmap))); + asid = mips_rd_entryhi(); + mips_wr_entryhi(hi); tlb_probe(); i = mips_rd_index(); if (i >= 0) { tlb_read(); - if ((va & PAGE_SIZE) == 0) { + if (even) { mips_wr_entrylo0(pte); } else { mips_wr_entrylo1(pte); } tlb_write_indexed(); + } else { + other = pte & PTE_G; + mips_wr_pagemask(0); + mips_wr_entryhi(hi); + if (even) { + mips_wr_entrylo0(pte); + mips_wr_entrylo1(other); + } else { + mips_wr_entrylo0(other); + mips_wr_entrylo1(pte); + } + tlb_write_random(); } mips_wr_entryhi(asid); [-- Attachment #4 --] Index: sys/mips/include/pte.h =================================================================== --- sys/mips/include/pte.h (revision 209521) +++ sys/mips/include/pte.h (working copy) @@ -73,7 +73,8 @@ * Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page. */ #define TLBHI_ASID_MASK (0xff) -#define TLBHI_ENTRY(va, asid) (((va) & ~PAGE_MASK) | ((asid) & TLBHI_ASID_MASK)) +#define TLBHI_PAGE_MASK (2 * PAGE_SIZE - 1) +#define TLBHI_ENTRY(va, asid) (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK)) #ifndef _LOCORE typedef uint32_t pt_entry_t; Index: sys/mips/mips/tlb.c =================================================================== --- sys/mips/mips/tlb.c (revision 209521) +++ sys/mips/mips/tlb.c (working copy) @@ -217,34 +217,43 @@ void tlb_update(struct pmap *pmap, vm_offset_t va, pt_entry_t pte) { - register_t mask, asid; + pt_entry_t other; + register_t asid, hi; register_t s; - int i; + int i, even; - va &= ~PAGE_MASK; + s = intr_disable(); + even = (va & PAGE_SIZE) == 0; pte &= ~TLBLO_SWBITS_MASK; - - s = intr_disable(); - mask = mips_rd_pagemask(); - asid = mips_rd_entryhi() & TLBHI_ASID_MASK; - - mips_wr_pagemask(0); - mips_wr_entryhi(TLBHI_ENTRY(va, pmap_asid(pmap))); + hi = TLBHI_ENTRY(va, pmap_asid(pmap)); + asid = mips_rd_entryhi(); + mips_wr_entryhi(hi); tlb_probe(); i = mips_rd_index(); if (i >= 0) { tlb_read(); - if ((va & PAGE_SIZE) == 0) { + if (even) { mips_wr_entrylo0(pte); } else { mips_wr_entrylo1(pte); } tlb_write_indexed(); + } else { + other = pte & PTE_G; + mips_wr_pagemask(0); + mips_wr_entryhi(hi); + if (even) { + mips_wr_entrylo0(pte); + mips_wr_entrylo1(other); + } else { + mips_wr_entrylo0(other); + mips_wr_entrylo1(pte); + } + tlb_write_random(); } mips_wr_entryhi(asid); - mips_wr_pagemask(mask); intr_restore(s); }
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