Date: Tue, 21 Aug 2018 08:14:11 +0300 From: Daniel Braniss <danny@cs.huji.ac.il> To: gljennjohn@gmail.com Cc: Mark Millard via freebsd-hackers <freebsd-hackers@freebsd.org>, Mark Millard <marklmi26-fbsd@yahoo.com>, Rajesh Kumar <rajfbsd@gmail.com>, freebsd-drivers@freebsd.org, Ian Lepore <ian@freebsd.org> Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD Message-ID: <9F8E2C3D-61D6-487E-A19D-6B91FBAD930B@cs.huji.ac.il> In-Reply-To: <20180820181322.71607854@ernst.home> References: <CAAO%2BANOXwXAzJt%2BBZez6422jqKjrKPboSe_%2BudnOCWxYqE-=sQ@mail.gmail.com> <1534523216.27158.17.camel@freebsd.org> <CAAO%2BANOs_YVov-d21Em1EHzajQw7wHsxkzZCnsZwkfBr2=mEiA@mail.gmail.com> <1534702861.27158.36.camel@freebsd.org> <BF721728-B6F5-4214-9180-B911D32D9FCA@cs.huji.ac.il> <A8202939-328A-4564-9CF5-F5F66F68B7B0@cs.huji.ac.il> <1534771095.27158.46.camel@freebsd.org> <35F2C250-B4CB-4C53-BF8F-43C338022E34@yahoo.com> <20180820181322.71607854@ernst.home>
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> On 20 Aug 2018, at 19:13, Gary Jennejohn <gljennjohn@gmail.com> wrote: > > On Mon, 20 Aug 2018 07:16:15 -0700 > Mark Millard via freebsd-hackers <freebsd-hackers@freebsd.org <mailto:freebsd-hackers@freebsd.org>> wrote: > >> On 2018-Aug-20, at 6:18 AM, Ian Lepore <ian at freebsd.org> wrote: >> >>> On Mon, 2018-08-20 at 11:13 +0300, Daniel Braniss wrote: >>>> >>>>> >>>>> On 20 Aug 2018, at 09:49, Daniel Braniss <danny@cs.huji.ac.il> wrote: >>>>> >>>>>> . . . >>>>> >>>>> hi, >>>>> I have similar issues with the allwinner/twsi but I do have a Saleae Logic and here is a nice picture: >>>> ah, maybe this is better: >>>> https://cs.huji.ac.il/~danny/Screen%20Shot%202018-08-20%20at%2011.06.43.png >>> . . . >>> This has nothing to do with the twsi driver, this is about the ig4 >>> driver (found in sys/dev/ichiic). >>> >>> That screenshot seems to show a bus running at 100KHz like it should >>> (although the 62:38 duty cycle is a bit suspicious). >> >> Being a logic analyzer display, it my just be that the threshold >> was off from the optimal value. The waveform shape is not really >> visible. >> >> The logic analyzer output also shows a thick "rising" edge without the >> uparrow symbol. My guess would be that is a rising/falling/rising >> sequence that on the scale in use does not show space between edges. In >> other words: a glitch on the leading edge side of the intended pulse. >> This too might be tied to the threshold used vs . the actual signal >> properties: no way to tell from what is shown. >> > > I have two of these logic analyzers and they definitely do a > major clean up of the signals displayed. > > Things like overshoot and ringing, which can be seen on an > oscilloscope, do not appear on what the logic analyzer displays. > > I suspect the purpose of the trace was simply to show the 100KHz > SCL. > yup, I connected the logic analyzer to check the frequency, which was not changing, later I confirmed by looking at the source that it’s set at a constant 100KHz. > -- > Gary Jennejohnhelp
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