Date: Mon, 12 May 2025 12:50:26 GMT From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: e4619b088dd0 - main - arm64: Add the ESR ISS value to struct mrs_user_reg Message-ID: <202505121250.54CCoQtV083032@gitrepo.freebsd.org>
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The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=e4619b088dd0853a3cf0841235d9576179b94d5b commit e4619b088dd0853a3cf0841235d9576179b94d5b Author: Andrew Turner <andrew@FreeBSD.org> AuthorDate: 2025-05-12 11:07:03 +0000 Commit: Andrew Turner <andrew@FreeBSD.org> CommitDate: 2025-05-12 11:07:03 +0000 arm64: Add the ESR ISS value to struct mrs_user_reg This will be used to compare against the ISS value from MSR/MRS exceptions. Reviewed by: harry.moulton_arm.com Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D50210 --- sys/arm64/arm64/identcpu.c | 2 ++ sys/arm64/include/armreg.h | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index 663c1a335114..c4eaaaafc279 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -2193,6 +2193,7 @@ static const struct mrs_field mvfr1_fields[] = { struct mrs_user_reg { u_int reg; + u_int iss; u_int CRm; u_int Op2; bool is64bit; @@ -2203,6 +2204,7 @@ struct mrs_user_reg { #define USER_REG(name, field_name, _is64bit) \ { \ .reg = name, \ + .iss = name##_ISS, \ .CRm = name##_CRm, \ .Op2 = name##_op2, \ .offset = __offsetof(struct cpu_desc, field_name), \ diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 8691e4b89649..a7950092048d 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -368,6 +368,7 @@ /* CTR_EL0 - Cache Type Register */ #define CTR_EL0 MRS_REG(CTR_EL0) #define CTR_EL0_REG MRS_REG_ALT_NAME(CTR_EL0) +#define CTR_EL0_ISS ISS_MSR_REG(CTR_EL0) #define CTR_EL0_op0 3 #define CTR_EL0_op1 3 #define CTR_EL0_CRn 0 @@ -768,6 +769,7 @@ /* ID_AA64AFR0_EL1 */ #define ID_AA64AFR0_EL1 MRS_REG(ID_AA64AFR0_EL1) #define ID_AA64AFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64AFR0_EL1) +#define ID_AA64AFR0_EL1_ISS ISS_MSR_REG(ID_AA64AFR0_EL1) #define ID_AA64AFR0_EL1_op0 3 #define ID_AA64AFR0_EL1_op1 0 #define ID_AA64AFR0_EL1_CRn 0 @@ -777,6 +779,7 @@ /* ID_AA64AFR1_EL1 */ #define ID_AA64AFR1_EL1 MRS_REG(ID_AA64AFR1_EL1) #define ID_AA64AFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64AFR1_EL1) +#define ID_AA64AFR1_EL1_ISS ISS_MSR_REG(ID_AA64AFR1_EL1) #define ID_AA64AFR1_EL1_op0 3 #define ID_AA64AFR1_EL1_op1 0 #define ID_AA64AFR1_EL1_CRn 0 @@ -786,6 +789,7 @@ /* ID_AA64DFR0_EL1 */ #define ID_AA64DFR0_EL1 MRS_REG(ID_AA64DFR0_EL1) #define ID_AA64DFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64DFR0_EL1) +#define ID_AA64DFR0_EL1_ISS ISS_MSR_REG(ID_AA64DFR0_EL1) #define ID_AA64DFR0_EL1_op0 3 #define ID_AA64DFR0_EL1_op1 0 #define ID_AA64DFR0_EL1_CRn 0 @@ -893,6 +897,7 @@ /* ID_AA64DFR1_EL1 */ #define ID_AA64DFR1_EL1 MRS_REG(ID_AA64DFR1_EL1) #define ID_AA64DFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64DFR1_EL1) +#define ID_AA64DFR1_EL1_ISS ISS_MSR_REG(ID_AA64DFR1_EL1) #define ID_AA64DFR1_EL1_op0 3 #define ID_AA64DFR1_EL1_op1 0 #define ID_AA64DFR1_EL1_CRn 0 @@ -920,6 +925,7 @@ /* ID_AA64ISAR0_EL1 */ #define ID_AA64ISAR0_EL1 MRS_REG(ID_AA64ISAR0_EL1) #define ID_AA64ISAR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR0_EL1) +#define ID_AA64ISAR0_EL1_ISS ISS_MSR_REG(ID_AA64ISAR0_EL1) #define ID_AA64ISAR0_EL1_op0 3 #define ID_AA64ISAR0_EL1_op1 0 #define ID_AA64ISAR0_EL1_CRn 0 @@ -1022,6 +1028,7 @@ /* ID_AA64ISAR1_EL1 */ #define ID_AA64ISAR1_EL1 MRS_REG(ID_AA64ISAR1_EL1) #define ID_AA64ISAR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR1_EL1) +#define ID_AA64ISAR1_EL1_ISS ISS_MSR_REG(ID_AA64ISAR1_EL1) #define ID_AA64ISAR1_EL1_op0 3 #define ID_AA64ISAR1_EL1_op1 0 #define ID_AA64ISAR1_EL1_CRn 0 @@ -1141,6 +1148,7 @@ /* ID_AA64ISAR2_EL1 */ #define ID_AA64ISAR2_EL1 MRS_REG(ID_AA64ISAR2_EL1) #define ID_AA64ISAR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR2_EL1) +#define ID_AA64ISAR2_EL1_ISS ISS_MSR_REG(ID_AA64ISAR2_EL1) #define ID_AA64ISAR2_EL1_op0 3 #define ID_AA64ISAR2_EL1_op1 0 #define ID_AA64ISAR2_EL1_CRn 0 @@ -1226,6 +1234,7 @@ /* ID_AA64MMFR0_EL1 */ #define ID_AA64MMFR0_EL1 MRS_REG(ID_AA64MMFR0_EL1) #define ID_AA64MMFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR0_EL1) +#define ID_AA64MMFR0_EL1_ISS ISS_MSR_REG(ID_AA64MMFR0_EL1) #define ID_AA64MMFR0_EL1_op0 3 #define ID_AA64MMFR0_EL1_op1 0 #define ID_AA64MMFR0_EL1_CRn 0 @@ -1333,6 +1342,7 @@ /* ID_AA64MMFR1_EL1 */ #define ID_AA64MMFR1_EL1 MRS_REG(ID_AA64MMFR1_EL1) #define ID_AA64MMFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR1_EL1) +#define ID_AA64MMFR1_EL1_ISS ISS_MSR_REG(ID_AA64MMFR1_EL1) #define ID_AA64MMFR1_EL1_op0 3 #define ID_AA64MMFR1_EL1_op1 0 #define ID_AA64MMFR1_EL1_CRn 0 @@ -1443,6 +1453,7 @@ /* ID_AA64MMFR2_EL1 */ #define ID_AA64MMFR2_EL1 MRS_REG(ID_AA64MMFR2_EL1) #define ID_AA64MMFR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR2_EL1) +#define ID_AA64MMFR2_EL1_ISS ISS_MSR_REG(ID_AA64MMFR2_EL1) #define ID_AA64MMFR2_EL1_op0 3 #define ID_AA64MMFR2_EL1_op1 0 #define ID_AA64MMFR2_EL1_CRn 0 @@ -1545,6 +1556,7 @@ /* ID_AA64MMFR3_EL1 */ #define ID_AA64MMFR3_EL1 MRS_REG(ID_AA64MMFR3_EL1) #define ID_AA64MMFR3_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR3_EL1) +#define ID_AA64MMFR3_EL1_ISS ISS_MSR_REG(ID_AA64MMFR3_EL1) #define ID_AA64MMFR3_EL1_op0 3 #define ID_AA64MMFR3_EL1_op1 0 #define ID_AA64MMFR3_EL1_CRn 0 @@ -1632,6 +1644,7 @@ /* ID_AA64MMFR4_EL1 */ #define ID_AA64MMFR4_EL1 MRS_REG(ID_AA64MMFR4_EL1) #define ID_AA64MMFR4_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR4_EL1) +#define ID_AA64MMFR4_EL1_ISS ISS_MSR_REG(ID_AA64MMFR4_EL1) #define ID_AA64MMFR4_EL1_op0 3 #define ID_AA64MMFR4_EL1_op1 0 #define ID_AA64MMFR4_EL1_CRn 0 @@ -1641,6 +1654,7 @@ /* ID_AA64PFR0_EL1 */ #define ID_AA64PFR0_EL1 MRS_REG(ID_AA64PFR0_EL1) #define ID_AA64PFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR0_EL1) +#define ID_AA64PFR0_EL1_ISS ISS_MSR_REG(ID_AA64PFR0_EL1) #define ID_AA64PFR0_EL1_op0 3 #define ID_AA64PFR0_EL1_op1 0 #define ID_AA64PFR0_EL1_CRn 0 @@ -1757,6 +1771,7 @@ /* ID_AA64PFR1_EL1 */ #define ID_AA64PFR1_EL1 MRS_REG(ID_AA64PFR1_EL1) #define ID_AA64PFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR1_EL1) +#define ID_AA64PFR1_EL1_ISS ISS_MSR_REG(ID_AA64PFR1_EL1) #define ID_AA64PFR1_EL1_op0 3 #define ID_AA64PFR1_EL1_op1 0 #define ID_AA64PFR1_EL1_CRn 0 @@ -1855,6 +1870,7 @@ /* ID_AA64PFR2_EL1 */ #define ID_AA64PFR2_EL1 MRS_REG(ID_AA64PFR2_EL1) #define ID_AA64PFR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR2_EL1) +#define ID_AA64PFR2_EL1_ISS ISS_MSR_REG(ID_AA64PFR2_EL1) #define ID_AA64PFR2_EL1_op0 3 #define ID_AA64PFR2_EL1_op1 0 #define ID_AA64PFR2_EL1_CRn 0 @@ -1864,6 +1880,7 @@ /* ID_AA64ZFR0_EL1 */ #define ID_AA64ZFR0_EL1 MRS_REG(ID_AA64ZFR0_EL1) #define ID_AA64ZFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64ZFR0_EL1) +#define ID_AA64ZFR0_EL1_ISS ISS_MSR_REG(ID_AA64ZFR0_EL1) #define ID_AA64ZFR0_EL1_op0 3 #define ID_AA64ZFR0_EL1_op1 0 #define ID_AA64ZFR0_EL1_CRn 0 @@ -1929,6 +1946,7 @@ /* ID_ISAR5_EL1 */ #define ID_ISAR5_EL1 MRS_REG(ID_ISAR5_EL1) +#define ID_ISAR5_EL1_ISS ISS_MSR_REG(ID_ISAR5_EL1) #define ID_ISAR5_EL1_op0 0x3 #define ID_ISAR5_EL1_op1 0x0 #define ID_ISAR5_EL1_CRn 0x0 @@ -2065,6 +2083,7 @@ /* MVFR0_EL1 */ #define MVFR0_EL1 MRS_REG(MVFR0_EL1) +#define MVFR0_EL1_ISS ISS_MSR_REG(MVFR0_EL1) #define MVFR0_EL1_op0 0x3 #define MVFR0_EL1_op1 0x0 #define MVFR0_EL1_CRn 0x0 @@ -2124,6 +2143,7 @@ /* MVFR1_EL1 */ #define MVFR1_EL1 MRS_REG(MVFR1_EL1) +#define MVFR1_EL1_ISS ISS_MSR_REG(MVFR1_EL1) #define MVFR1_EL1_op0 0x3 #define MVFR1_EL1_op1 0x0 #define MVFR1_EL1_CRn 0x0
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