Date: Tue, 26 Feb 2008 16:40:00 GMT From: "Randall R. Stewart" <rrs@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 136268 for review Message-ID: <200802261640.m1QGe0wd053703@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=136268 Change 136268 by rrs@rrs-mips2-jnpr on 2008/02/26 16:39:52 Move to mips64r2 and do mips0 for restoral Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/psraccess.S#7 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/psraccess.S#7 (text+ko) ==== @@ -120,16 +120,10 @@ LEAF(enableintr) #ifdef TARGET_OCTEON - .set mips64 - .word 0x041626020 #ei v0 + .set mips64r2 + ei v0 and v0, SR_INT_ENAB # return old interrupt enable bit -#if defined(ISA_MIPS32) - .set mips32 -#elif defined(ISA_MIPS64) - .set mips64 -#elif defined(ISA_MIPS3) - .set mips3 -#endif + .set mips0 #else mfc0 v0, COP_0_STATUS_REG # read status register nop @@ -144,16 +138,10 @@ LEAF(disableintr) #ifdef TARGET_OCTEON - .set mips64 - .word 0x041626000 #di v0 + .set mips64r2 + di v0 and v0, SR_INT_ENAB # return old interrupt enable bit -#if defined(ISA_MIPS32) - .set mips32 -#elif defined(ISA_MIPS64) - .set mips64 -#elif defined(ISA_MIPS3) - .set mips3 -#endif + .set mips0 #else mfc0 v0, COP_0_STATUS_REG # read status register and v0, v0, SR_INT_ENAB
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