Date: Thu, 20 Feb 2014 23:17:46 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r262271 - projects/arm64/sys/arm64/include Message-ID: <201402202317.s1KNHkDc007830@svn.freebsd.org>
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Author: andrew Date: Thu Feb 20 23:17:46 2014 New Revision: 262271 URL: http://svnweb.freebsd.org/changeset/base/262271 Log: Add more ARM registers Modified: projects/arm64/sys/arm64/include/armreg.h Modified: projects/arm64/sys/arm64/include/armreg.h ============================================================================== --- projects/arm64/sys/arm64/include/armreg.h Thu Feb 20 23:17:24 2014 (r262270) +++ projects/arm64/sys/arm64/include/armreg.h Thu Feb 20 23:17:46 2014 (r262271) @@ -29,6 +29,10 @@ #ifndef _MACHINE_ARMREG_H_ #define _MACHINE_ARMREG_H_ +/* Memory Attribute Indirection register */ +/* TODO: Should this be in a pte header? */ +#define MAIR(attr, idx) ((attr) << ((idx) * 8)) + /* * The various *PSR registers, e.g. cpsr or cpsr. * @@ -81,4 +85,24 @@ #define SCTLR_EE 0x02000000 #define SCTLR_UCI 0x04000000 +/* Translation Control Register */ +#define TCR_ASID_16 (1 << 36) + +#define TCR_IPS_SHIFT 32 +#define TCR_IPS_32BIT (0 << TCR_IPS_SHIFT) +#define TCR_IPS_36BIT (1 << TCR_IPS_SHIFT) +#define TCR_IPS_40BIT (2 << TCR_IPS_SHIFT) +#define TCR_IPS_42BIT (3 << TCR_IPS_SHIFT) +#define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT) +#define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT) + +#define TCR_TG1_SHIFT 30 +#define TCR_TG1_16K (1 << TCR_TG1_SHIFT) +#define TCR_TG1_4K (2 << TCR_TG1_SHIFT) +#define TCR_TG1_64K (3 << TCR_TG1_SHIFT) + +#define TCR_T1SZ_SHIFT 16 +#define TCR_T0SZ_SHIFT 0 +#define TCR_TxSZ(x) (((x) << TCR_T1SZ_SHIFT) | ((x) << TCR_T0SZ_SHIFT)) + #endif
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