Date: Sun, 17 Feb 2008 19:09:55 +0200 From: Andriy Gapon <avg@icyb.net.ua> To: Erich Dollansky <oceanare@pacific.net.sg> Cc: freebsd-hackers@freebsd.org Subject: Re: multiple interrupts between cli and sti Message-ID: <47B86A63.1040205@icyb.net.ua> In-Reply-To: <47B85E92.9010206@pacific.net.sg> References: <47B855C0.4010703@icyb.net.ua> <47B85E92.9010206@pacific.net.sg>
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on 17/02/2008 18:19 Erich Dollansky said the following: > Hi, > > Andriy Gapon wrote: > > I cannot tell you if this is still the same for modern designs. > >> ... -> iret -> interrupted again > > This was the behaviour earlier. >> Is this a deterministic behavior ? Or some timings are at play? > > The PIC should never release the Interrupt signal to the CPU as long as > a single interrupt is not serviced. > > But the 8259 can be programmed to trigger via level or slope. > > So, this behaviour is only seen when level triggering is used. > > As I said at the bginning, I do not know how current designs handle it. But I thought level/edge thing is about interrupts between devices and PIC, not between PIC and CPU. I might be confused, though. -- Andriy Gapon
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