Date: Wed, 14 Aug 2019 16:40:23 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r351029 - in stable/12/sys/arm64: arm64 include Message-ID: <201908141640.x7EGeNpc034196@repo.freebsd.org>
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Author: andrew Date: Wed Aug 14 16:40:23 2019 New Revision: 351029 URL: https://svnweb.freebsd.org/changeset/base/351029 Log: MFC r339592: Correctly set the DAIF bits in new threads We should only unmask interrupts when creating a new thread and leave the other exceptions in teh same state as before creating the thread. Modified: stable/12/sys/arm64/arm64/vm_machdep.c stable/12/sys/arm64/include/armreg.h Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/arm64/arm64/vm_machdep.c ============================================================================== --- stable/12/sys/arm64/arm64/vm_machdep.c Wed Aug 14 16:12:03 2019 (r351028) +++ stable/12/sys/arm64/arm64/vm_machdep.c Wed Aug 14 16:40:23 2019 (r351029) @@ -111,7 +111,7 @@ cpu_fork(struct thread *td1, struct proc *p2, struct t /* Setup to release spin count in fork_exit(). */ td2->td_md.md_spinlock_count = 1; - td2->td_md.md_saved_daif = 0; + td2->td_md.md_saved_daif = td1->td_md.md_saved_daif & ~DAIF_I_MASKED; } void @@ -182,7 +182,7 @@ cpu_copy_thread(struct thread *td, struct thread *td0) /* Setup to release spin count in fork_exit(). */ td->td_md.md_spinlock_count = 1; - td->td_md.md_saved_daif = 0; + td->td_md.md_saved_daif = td0->td_md.md_saved_daif & ~DAIF_I_MASKED; } /* Modified: stable/12/sys/arm64/include/armreg.h ============================================================================== --- stable/12/sys/arm64/include/armreg.h Wed Aug 14 16:12:03 2019 (r351028) +++ stable/12/sys/arm64/include/armreg.h Wed Aug 14 16:40:23 2019 (r351029) @@ -66,6 +66,12 @@ #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) #define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) +/* DAIF - Interrupt Mask Bits */ +#define DAIF_D_MASKED (1 << 9) +#define DAIF_A_MASKED (1 << 8) +#define DAIF_I_MASKED (1 << 7) +#define DAIF_F_MASKED (1 << 6) + /* DCZID_EL0 - Data Cache Zero ID register */ #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ #define DCZID_BS_SHIFT 0
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