Date: Thu, 13 Mar 2008 20:25:02 GMT From: Marcel Moolenaar <marcel@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 137641 for review Message-ID: <200803132025.m2DKP2Hj008730@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=137641 Change 137641 by marcel@marcel_jnpr on 2008/03/13 20:24:52 Revert to vendor. The implementation is in sys/powerpc/booke/machdep.c Affected files ... .. //depot/projects/e500/sys/powerpc/powerpc/cpu.c#5 edit Differences ... ==== //depot/projects/e500/sys/powerpc/powerpc/cpu.c#5 (text+ko) ==== @@ -112,9 +112,6 @@ static void cpu_print_speed(void); static void cpu_config_l2cr(u_int, uint16_t); -extern void icache_enable(void); -extern void dcache_enable(void); - void cpu_setup(u_int cpuid) { @@ -266,28 +263,6 @@ printf("\n"); cpu_config_l2cr(cpuid, vers); break; - case FSL_E500v1: - case FSL_E500v2: -#if 0 - /* - * Cache enable sequence according - * to section 2.16 of E500CORE RM. - */ - printf("L1 CSR0 (d): 0x%08x\n", mfspr(SPR_L1CSR0)); - printf("L1 CSR1 (i): 0x%08x\n", mfspr(SPR_L1CSR1)); - - printf("Enable i/d-cache...\n"); - - /* Enable d-cache */ - dcache_enable(); - - /* Enable i-cache */ - icache_enable(); - printf("L1 CSR0 (d): 0x%08x\n", mfspr(SPR_L1CSR0)); - printf("L1 CSR1 (i): 0x%08x\n", mfspr(SPR_L1CSR1)); -#endif - printf("\n"); - break; default: printf("\n"); break;help
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