Date: Sat, 28 Jul 2018 12:50:09 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r336829 - in head/sys: arm/arm conf Message-ID: <201807281250.w6SCo9VX090259@repo.freebsd.org>
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Author: andrew Date: Sat Jul 28 12:50:09 2018 New Revision: 336829 URL: https://svnweb.freebsd.org/changeset/base/336829 Log: Only build the cache handling code we need when building the arm ELF trampoline. Modified: head/sys/arm/arm/cpufunc_asm_armv5_ec.S head/sys/arm/arm/cpufunc_asm_sheeva.S head/sys/conf/Makefile.arm Modified: head/sys/arm/arm/cpufunc_asm_armv5_ec.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_armv5_ec.S Sat Jul 28 12:20:42 2018 (r336828) +++ head/sys/arm/arm/cpufunc_asm_armv5_ec.S Sat Jul 28 12:50:09 2018 (r336829) @@ -39,6 +39,7 @@ #include <machine/asm.h> __FBSDID("$FreeBSD$"); +#ifndef ELF_TRAMPOLINE /* * Functions to set the MMU Translation Table Base register * @@ -192,6 +193,7 @@ ENTRY(armv5_ec_idcache_wbinv_range) mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ RET END(armv5_ec_idcache_wbinv_range) +#endif /* !ELF_TRAMPOLINE */ ENTRY_NP(armv5_ec_idcache_wbinv_all) .Larmv5_ec_idcache_wbinv_all: @@ -204,6 +206,7 @@ ENTRY_NP(armv5_ec_idcache_wbinv_all) /* Fall through to purge Dcache. */ END(armv5_ec_idcache_wbinv_all) +#ifndef ELF_TRAMPOLINE ENTRY(armv5_ec_dcache_wbinv_all) .Larmv5_ec_dcache_wbinv_all: 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */ @@ -211,4 +214,4 @@ ENTRY(armv5_ec_dcache_wbinv_all) mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ RET END(armv5_ec_dcache_wbinv_all) - +#endif Modified: head/sys/arm/arm/cpufunc_asm_sheeva.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_sheeva.S Sat Jul 28 12:20:42 2018 (r336828) +++ head/sys/arm/arm/cpufunc_asm_sheeva.S Sat Jul 28 12:50:09 2018 (r336829) @@ -35,6 +35,7 @@ __FBSDID("$FreeBSD$"); #include <machine/armreg.h> #include <machine/param.h> +#ifndef ELF_TRAMPOLINE .Lsheeva_cache_line_size: .word _C_LABEL(arm_pdcache_line_size) .Lsheeva_asm_page_mask: @@ -376,6 +377,7 @@ ENTRY(sheeva_l2cache_wb_range) ldr lr, [sp], #4 RET END(sheeva_l2cache_wb_range) +#endif /* !ELF_TRAMPOLINE */ ENTRY(sheeva_l2cache_wbinv_all) /* Disable irqs */ @@ -393,6 +395,7 @@ ENTRY(sheeva_l2cache_wbinv_all) RET END(sheeva_l2cache_wbinv_all) +#ifndef ELF_TRAMPOLINE /* This function modifies register value as follows: * * arg1 arg EFFECT (bit value saved into register) @@ -418,4 +421,4 @@ ENTRY(sheeva_cpu_sleep) mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt */ mov pc, lr END(sheeva_cpu_sleep) - +#endif /* !ELF_TRAMPOLINE */ Modified: head/sys/conf/Makefile.arm ============================================================================== --- head/sys/conf/Makefile.arm Sat Jul 28 12:20:42 2018 (r336828) +++ head/sys/conf/Makefile.arm Sat Jul 28 12:50:09 2018 (r336829) @@ -73,8 +73,6 @@ SYSTEM_LD_TAIL +=;sed s/" + SIZEOF_HEADERS"// ldscript rm ${FULLKERNEL}.noheader FILES_CPU_FUNC = \ - $S/$M/$M/cpufunc_asm_arm9.S \ - $S/$M/$M/cpufunc_asm.S \ $S/$M/$M/cpufunc_asm_armv5_ec.S \ $S/$M/$M/cpufunc_asm_sheeva.S
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