Date: Mon, 25 Apr 2016 13:20:57 +0000 (UTC) From: Ruslan Bukin <br@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r298578 - in head/sys: conf riscv/riscv Message-ID: <201604251320.u3PDKvsJ057815@repo.freebsd.org>
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Author: br Date: Mon Apr 25 13:20:57 2016 New Revision: 298578 URL: https://svnweb.freebsd.org/changeset/base/298578 Log: Revert r298477 ("Clear the DDR memory"). There is no need to clear all the DDR memory (we only need to clear BSS section). I was playing with non-default version of hardware (the bitfile synthesized for 4-level page memory system) and clearing was helpful, but then realized support for 4-level page system is untested/broken in both RocketCore and lowRISC. Modified: head/sys/conf/options.riscv head/sys/riscv/riscv/locore.S Modified: head/sys/conf/options.riscv ============================================================================== --- head/sys/conf/options.riscv Mon Apr 25 13:20:35 2016 (r298577) +++ head/sys/conf/options.riscv Mon Apr 25 13:20:57 2016 (r298578) @@ -2,4 +2,3 @@ RISCV opt_global.h VFP opt_global.h -DDR_CLEAR_SIZE opt_global.h Modified: head/sys/riscv/riscv/locore.S ============================================================================== --- head/sys/riscv/riscv/locore.S Mon Apr 25 13:20:35 2016 (r298577) +++ head/sys/riscv/riscv/locore.S Mon Apr 25 13:20:57 2016 (r298578) @@ -126,17 +126,6 @@ _start: csrr a0, mhartid bnez a0, mpentry -#if defined(DDR_CLEAR_SIZE) - /* Clear DDR memory */ - la t0, _end - li t1, DDR_CLEAR_SIZE -1: - sd zero, 0(t0) - addi t0, t0, 8 - bltu t0, t1, 1b - /* End */ -#endif - /* Build event queue for current core */ build_ring
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