Date: Mon, 25 Apr 2016 13:30:37 +0000 (UTC) From: Ruslan Bukin <br@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r298579 - head/sys/riscv/riscv Message-ID: <201604251330.u3PDUbM3060757@repo.freebsd.org>
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Author: br Date: Mon Apr 25 13:30:37 2016 New Revision: 298579 URL: https://svnweb.freebsd.org/changeset/base/298579 Log: Do not setup machine exception vector. Sounds strange, but both RocketCore and lowRISC do not operate if we set it. All the known implementations (Spike, QEMU, RocketCore, lowRISC) uses default machine trap vector address and operates fine with this. Original Berkeley Boot Loader (bbl) does not set this as well. Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Modified: head/sys/riscv/riscv/locore.S Modified: head/sys/riscv/riscv/locore.S ============================================================================== --- head/sys/riscv/riscv/locore.S Mon Apr 25 13:20:57 2016 (r298578) +++ head/sys/riscv/riscv/locore.S Mon Apr 25 13:30:37 2016 (r298579) @@ -133,9 +133,6 @@ _start: la t0, hardstack_end csrw mscratch, t0 - la t0, mentry - csrw mtvec, t0 - li t0, 0 csrw sscratch, t0 @@ -335,10 +332,6 @@ ENTRY(mpentry) lw t1, 0(t0) beqz t1, 1b - /* Setup machine exception vector */ - la t0, mentry - csrw mtvec, t0 - /* Build event queue ring for this core */ build_ring
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