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Date:      Sun, 28 May 2017 12:05:16 +0000 (UTC)
From:      Michael Zhilin <mizhka@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r319069 - in head/sys: dev/bhnd/cores/chipc dev/bhnd/cores/chipc/pwrctl mips/broadcom
Message-ID:  <201705281205.v4SC5G9t078564@repo.freebsd.org>
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Author: mizhka
Date: Sun May 28 12:05:16 2017
New Revision: 319069
URL: https://svnweb.freebsd.org/changeset/base/319069

Log:
  [mips] [bhnd] Support of old PMU for BMIPS and siba SoC
  
   - Fix typo of PLL Type 4
   - Don't panic of frequency getters
  
  Submitted by:	Hiroki Mori <yamori813@yahoo.co.jp>
  Differential Revision:	https://reviews.freebsd.org/D10967

Modified:
  head/sys/dev/bhnd/cores/chipc/chipcreg.h
  head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
  head/sys/mips/broadcom/bcm_pmu.c

Modified: head/sys/dev/bhnd/cores/chipc/chipcreg.h
==============================================================================
--- head/sys/dev/bhnd/cores/chipc/chipcreg.h	Sun May 28 10:46:34 2017	(r319068)
+++ head/sys/dev/bhnd/cores/chipc/chipcreg.h	Sun May 28 12:05:16 2017	(r319069)
@@ -280,7 +280,7 @@ enum {
 #define	CHIPC_PLL_TYPE1		0x2	/* 48MHz base, 3 dividers */
 #define	CHIPC_PLL_TYPE2		0x4	/* 48MHz, 4 dividers */
 #define	CHIPC_PLL_TYPE3		0x6	/* 25MHz, 2 dividers */
-#define	CHIPC_PLL_TYPE4		0x8	/* 48MHz, 4 dividers */
+#define	CHIPC_PLL_TYPE4		0x1	/* 48MHz, 4 dividers */
 #define	CHIPC_PLL_TYPE5		0x3	/* 25MHz, 4 dividers */
 #define	CHIPC_PLL_TYPE6		0x5	/* 100/200 or 120/240 only */
 #define	CHIPC_PLL_TYPE7		0x7	/* 25MHz, 4 dividers */

Modified: head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
==============================================================================
--- head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c	Sun May 28 10:46:34 2017	(r319068)
+++ head/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c	Sun May 28 12:05:16 2017	(r319069)
@@ -374,7 +374,7 @@ bhnd_pwrctl_slowclk_freq(struct bhnd_pwr
 	} else if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) {
 		div = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL);
 		div = CHIPC_GET_BITS(div, CHIPC_SCC_CD);
-		div *= 4;
+		div = 4 * (div + 1);
 	} else if (PWRCTL_QUIRK(sc, INSTACLK_CTL)) {
 		if (max_freq) {
 			div = 1;
@@ -503,7 +503,10 @@ bhnd_pwrctl_setclk(struct bhnd_pwrctl_so
 	if (bhnd_get_hwrev(sc->chipc_dev) == 10)
 		return (ENODEV);
 
-	scc = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL);
+	if (PWRCTL_QUIRK(sc, SLOWCLK_CTL))
+		scc = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL);
+	else
+		scc = bhnd_bus_read_4(sc->res, CHIPC_SYS_CLK_CTL);
 
 	switch (clock) {
 	case BHND_CLOCK_HT:
@@ -520,7 +523,10 @@ bhnd_pwrctl_setclk(struct bhnd_pwrctl_so
 			return (ENODEV);
 		}
 
-		bhnd_bus_write_4(sc->res, CHIPC_PLL_SLOWCLK_CTL, scc);
+		if (PWRCTL_QUIRK(sc, SLOWCLK_CTL))
+			bhnd_bus_write_4(sc->res, CHIPC_PLL_SLOWCLK_CTL, scc);
+		else
+			bhnd_bus_write_4(sc->res, CHIPC_SYS_CLK_CTL, scc);
 		DELAY(CHIPC_PLL_DELAY);
 
 		break;		

Modified: head/sys/mips/broadcom/bcm_pmu.c
==============================================================================
--- head/sys/mips/broadcom/bcm_pmu.c	Sun May 28 10:46:34 2017	(r319068)
+++ head/sys/mips/broadcom/bcm_pmu.c	Sun May 28 12:05:16 2017	(r319069)
@@ -208,7 +208,7 @@ bcm_get_uart_rclk(struct bcm_platform *b
 uint64_t
 bcm_get_alpfreq(struct bcm_platform *bp) {
 	if (!bcm_has_pmu(bp))
-		panic("%s requires PMU\n", __FUNCTION__);
+		return (BHND_PMU_ALP_CLOCK);
 
 	return (bhnd_pmu_alp_clock(bcm_get_pmu(bp)));
 }
@@ -217,7 +217,7 @@ bcm_get_alpfreq(struct bcm_platform *bp)
 uint64_t
 bcm_get_ilpfreq(struct bcm_platform *bp) {
 	if (!bcm_has_pmu(bp))
-		panic("%s requires PMU\n", __FUNCTION__);
+		return (BHND_PMU_ILP_CLOCK);
 
 	return (bhnd_pmu_ilp_clock(bcm_get_pmu(bp)));
 }

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