Date: Sun, 21 Mar 2010 00:13:11 +0000 (UTC) From: Alan Cox <alc@FreeBSD.org> To: cvs-src-old@freebsd.org Subject: cvs commit: src/sys/amd64/amd64 mca.c src/sys/amd64/include specialreg.h Message-ID: <201003210019.o2L0JGDw099630@repoman.freebsd.org>
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alc 2010-03-21 00:13:11 UTC
FreeBSD src repository
Modified files:
sys/amd64/amd64 mca.c
sys/amd64/include specialreg.h
Log:
SVN rev 205402 on 2010-03-21 00:13:11Z by alc
I am told by AMD that the machine check hardware on the instruction TLB
won't generate bogus exceptions. Therefore, the implementation of the
"unofficial" workaround needn't mask L1TP errors by the instruction cache
unit.
Revision Changes Path
1.10 +4 -7 src/sys/amd64/amd64/mca.c
1.60 +0 -1 src/sys/amd64/include/specialreg.h
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