Date: Sat, 17 Aug 1996 22:44:14 +0200 (MET DST) From: J Wunsch <j@uriah.heep.sax.de> To: freebsd-current@FreeBSD.org (FreeBSD-current users) Cc: staff@kyklopen.ping.dk Subject: Re: 82439HX registerdump patch Message-ID: <199608172044.WAA01189@uriah.heep.sax.de> In-Reply-To: <Pine.BSI.3.95.960817171857.2351A-100000@kyklopen> from Thomas Sparrevohn at "Aug 17, 96 05:20:35 pm"
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As Thomas Sparrevohn wrote:
> + { 0x00, 0x00, 0x00, M_TR, ",\n\tDRAM Refrest Rate " },
Refresh
Here's my dmesg output, it's an ASUS P/I-P55T2P4 board.
Btw., i had to bump the message buffer size to two pages -- David,
didn't we intend to make this the default?
chip0 <Intel 82439HX (Triton II) PCI cache memory controller> rev 1 on pci0:0
DRAM ECC/Parity: ECC, ECC Test disabled,
Shutdown to Port 92 disabled, Dual Processor NA# disabled,
Peer Concurrency enabled, SERR# Output Type: Open drain output,
Global TXC enabled
Cache: 512K dual-bank pipelined-burst, NA Disable: disabled,
Extended Cacheability disabled, SCFMI disabled, L1 enabled
Speculative Leadoff disabled, Turn-around Insertion disabled,
Memory Address Drive Strength: 8mA/8mA, 64 Mbit mode disabled
Hole: None, EDO Detect mode disabled,
DRAM Refrest Rate 66Mhz
Turbo Read Leadoff disabled,
DRAM Read Burst Timing: x-3-3-3/x-4-4-4,
DRAM Write Burst Timing: x-3-3-3,
Fast RAS to CAS Delay: 3 clocks,
DRAM leadoff Timing: Read 7, Write 6, Precharge 4, Refresh 5
--
cheers, J"org
joerg_wunsch@uriah.heep.sax.de -- http://www.sax.de/~joerg/ -- NIC: JW11-RIPE
Never trust an operating system you don't have sources for. ;-)
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