Date: Mon, 5 Nov 2012 09:01:09 -0800 From: Stanislav Sedov <stas@freebsd.org> To: Warner Losh <imp@bsdimp.com> Cc: "Rodney W. Grimes" <freebsd@pdx.rh.cn85.chatusa.com>, Juli Mallett <juli@clockworksquid.com>, "freebsd-mips@FreeBSD.org" <freebsd-mips@freebsd.org> Subject: Re: CACHE_LINE_SIZE macro. Message-ID: <2427F526-B96B-49C2-ACCB-4AA51BDCB0D6@freebsd.org> In-Reply-To: <DAE462F0-9D85-4942-8826-C0709E36D3B7@bsdimp.com> References: <CACVs6=_BrwJ19CPj7OqKvV8boHfujVWqn96u3VPUmZ040JpAeQ@mail.gmail.com> <201211041828.qA4ISomC076058@pdx.rh.CN85.ChatUSA.com> <CAF6rxgn-bNJOuvdiRj_UUGQUTRaeOt54OdzHOioNz5f566hoig@mail.gmail.com> <DAE462F0-9D85-4942-8826-C0709E36D3B7@bsdimp.com>
index | next in thread | previous in thread | raw e-mail
On Nov 5, 2012, at 8:49 AM, Warner Losh <imp@bsdimp.com> wrote: > > Is that an out-of-kernel interface? > > If we did that, we'd have to make it run-time settable, because there's no one right answer for arm and MIPS cpus: they are all different. > IIRC, several linux application use getconf to retrieve the host CPU cache line value at the compile time to use for the alignment. I don't really like this solution as it makes the binaries unportable between different CPUs. OTOH, it looks like at least for ARM all cpus with a certain ARM core share the same cache line size, and we don't guarantee that e.g. ARMv5 executable will be able to run on ARMv7 without performance penalty. So it might be a good solution for ARM. I don't know about MIPS though. -- ST4096-RIPEhome | help
Want to link to this message? Use this
URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?2427F526-B96B-49C2-ACCB-4AA51BDCB0D6>