Date: Tue, 14 Sep 2010 11:03:52 +0530 From: "Jayachandran C." <c.jayachandran@gmail.com> To: Neel Natu <neelnatu@gmail.com> Cc: freebsd-mips@freebsd.org Subject: Re: PATCH: make usage of set_intr_mask() sane Message-ID: <AANLkTikmi6UC2sSHj45dzDRRrC1Z-8C%2Bzr1fhbovPVqJ@mail.gmail.com> In-Reply-To: <AANLkTimsZuEOkGLq2jOaY9ZSkm=oEmSHDQ8GxWVRr7qg@mail.gmail.com>
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On Tue, Sep 14, 2010 at 7:37 AM, Neel Natu <neelnatu@gmail.com> wrote:
> Hi,
>
> This patch changes the meaning of the 'mask' argument to
> 'set_intr_mask(mask)' to exactly match the meaning of the IM0..7 bits
> in the CP0 status register.
>
> The way we have it set up right now is exactly the opposite for no
> good reason IMHO.
>
> Please review and let me know if there are any objections.
This is something I thought about doing with the last patch - so I
would like to see this go in.
But I think the reason probably is that on MIPS setting interrupt mask
bit to 1 enables the interrupt, instead of masking (disabling) it.
JC.
> best
> Neel
>
> Index: sys/mips/sibyte/sb_machdep.c
> ===================================================================
> --- sys/mips/sibyte/sb_machdep.c (revision 212587)
> +++ sys/mips/sibyte/sb_machdep.c (working copy)
> @@ -370,7 +370,7 @@
> */
> clock_int_mask = hard_int_mask(5);
> ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
> - set_intr_mask(MIPS_SR_INT_MASK & ~(ipi_int_mask | clock_int_mask));
> + set_intr_mask(ipi_int_mask | clock_int_mask);
> }
>
> int
> Index: sys/mips/include/cpufunc.h
> ===================================================================
> --- sys/mips/include/cpufunc.h (revision 212587)
> +++ sys/mips/include/cpufunc.h (working copy)
> @@ -272,7 +272,7 @@
> uint32_t ostatus;
>
> ostatus = mips_rd_status();
> - mask = (ostatus & ~MIPS_SR_INT_MASK) | (~mask & MIPS_SR_INT_MASK);
> + mask = (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_INT_MASK);
> mips_wr_status(mask);
> return (ostatus);
> }
> Index: sys/mips/cavium/octeon_mp.c
> ===================================================================
> --- sys/mips/cavium/octeon_mp.c (revision 212587)
> +++ sys/mips/cavium/octeon_mp.c (working copy)
> @@ -96,7 +96,7 @@
> */
> clock_int_mask = hard_int_mask(5);
> ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
> - set_intr_mask(MIPS_SR_INT_MASK & ~(ipi_int_mask | clock_int_mask));
> + set_intr_mask(ipi_int_mask | clock_int_mask);
>
> mips_wbflush();
> }
> Index: sys/mips/mips/machdep.c
> ===================================================================
> --- sys/mips/mips/machdep.c (revision 212587)
> +++ sys/mips/mips/machdep.c (working copy)
> @@ -356,7 +356,7 @@
> * Mask all interrupts. Each interrupt will be enabled
> * when handler is installed for it
> */
> - set_intr_mask(MIPS_SR_INT_MASK);
> + set_intr_mask(0);
>
> /* Clear BEV in SR so we start handling our own exceptions */
> mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
> Index: sys/mips/mips/trap.c
> ===================================================================
> --- sys/mips/mips/trap.c (revision 212587)
> +++ sys/mips/mips/trap.c (working copy)
> @@ -304,7 +304,7 @@
> * return to userland.
> */
> if (trapframe->sr & MIPS_SR_INT_IE) {
> - set_intr_mask(~(trapframe->sr & MIPS_SR_INT_MASK));
> + set_intr_mask(trapframe->sr & MIPS_SR_INT_MASK);
> intr_enable();
> } else {
> intr_disable();
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