Date: Wed, 12 Sep 2001 15:07:00 GMT From: "J. Goodleaf" <john@goodleaf.net> To: hardware@freebsd.org Subject: optimizations for P4? Message-ID: <20010912150700.C915F5C77@clyde.goodleaf.net>
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Didn't see a thread specifically about this in search of mailing lists, so I thought I'd ask. Am eyeballing the forthcoming P4 motherboards based on the VIA DDR chipset. My question: Given the many advancements over the P6 cores we're accustomed to, are there any compiler optimizations I can use when building world that will allow a reasonably full expression of the processor's potential? I ask because many early P4 benchmarks showed a distinct tendency for the P4 to do better when applications were compiled specifically for it. (See the controversy among several hardware site content providers on audio encoding a few months back.) I expect that the P4 will work with no trouble under a gcc buildworld, but will it be using those famous double-pumped ALUs (etc.) as well as it could? If not, I may as well go with AMD or PIIIs... Thx, J To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hardware" in the body of the message
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