Date: Mon, 14 Jun 2004 22:42:37 GMT From: Juli Mallett <jmallett@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 54960 for review Message-ID: <200406142242.i5EMgbnS042203@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=54960 Change 54960 by jmallett@jmallett_oingo on 2004/06/14 22:42:18 Go back to cute AND'ing of bits. Looks like this may actually be a requirement for at least one of my systems, or I'm on crack. Affected files ... .. //depot/projects/mips/sys/mips/mips/locore.S#14 edit Differences ... ==== //depot/projects/mips/sys/mips/mips/locore.S#14 (text+ko) ==== @@ -54,19 +54,27 @@ GLOBAL(btext) ENTRY(start) /* - * t0: Bits to set: + * t0: Bits to preserve if set: + * Soft reset + * Boot exception vectors (firmware-provided) + */ + li t0, MIPS_SR_BEV | MIPS_SR_SR + /* + * t1: Bits to set explicitly: * Kernel mode is 64-bit * Enable FPU */ - li t0, MIPS_SR_KX | MIPS_SR_COP_1_BIT + li t1, MIPS_SR_KX | MIPS_SR_COP_1_BIT /* - * Read coprocessor 0 status register, and set bits we want to - * explicitly set. + * Read coprocessor 0 status register, clear bits not + * preserved (namely, clearing interrupt bits), and set + * bits we want to explicitly set. */ - mfc0 t1, MIPS_COP_0_STATUS - or t1, t0 - mtc0 t1, MIPS_COP_0_STATUS + mfc0 t2, MIPS_COP_0_STATUS + and t2, t0 + or t2, t1 + mtc0 t2, MIPS_COP_0_STATUS COP0_SYNC /* Extra nops for the FPU to spin up. */
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