Date: Fri, 1 May 2009 17:05:49 +0000 (UTC) From: Alexander Motin <mav@FreeBSD.org> To: cvs-src-old@freebsd.org Subject: cvs commit: src/sys/amd64/amd64 local_apic.c src/sys/i386/i386 local_apic.c Message-ID: <200905011706.n41H6AnK089105@repoman.freebsd.org>
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mav 2009-05-01 17:05:49 UTC
FreeBSD src repository
Modified files:
sys/amd64/amd64 local_apic.c
sys/i386/i386 local_apic.c
Log:
SVN rev 191720 on 2009-05-01 17:05:49Z by mav
Use value -1 instead of 0 for marking unused APIC vectors. This fixes
IRQ0 routing on LAPIC-enabled systems.
Add hint.apic.0.clock tunable. Setting it 0 disables using LAPIC timers
as hard-/stat-/profclock sources falling back to using i8254 and rtc timers.
On modern CPUs LAPIC is a part of CPU core which is shutting down when CPU
enters C3 or deeper power state. It makes no problems for interrupt
processing, as chipset wakes up CPU on interrupt triggering. But entering
C3 state kills LAPIC timer and freezes system time, making C3 and deeper
states practically unusable. Using i8254 timer allows to avoid this
problem.
By using i8254 timer my T7700 C2D CPU with UP kernel successfully enters
C3 state, saving more then a Watt of total idle power (>10%) in addition to
all other power-saving techniques.
This technique is not working for SMP yet, as only one CPU receives
timer interrupts. But I think that problem could be fixed by forwarding
interrupts to other CPUs with IPI.
Revision Changes Path
1.53 +11 -5 src/sys/amd64/amd64/local_apic.c
1.56 +11 -5 src/sys/i386/i386/local_apic.c
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