Date: Mon, 7 Oct 1996 23:22:11 +0000 (GMT) From: Adam David <adam@veda.is> To: dyson@freebsd.org Cc: guido@gvr.win.tue.nl, dyson@freebsd.org, dyson@freefall.freebsd.org, CVS-committers@freefall.freebsd.org, cvs-all@freefall.freebsd.org, cvs-sys@freefall.freebsd.org Subject: Re: cvs commit: src/sys/vm vm_page.h Message-ID: <199610072322.XAA06650@veda.is> In-Reply-To: <199610072234.RAA03072@dyson.iquest.net> from "John S. Dyson" at "Oct 7, 96 05:34:26 pm"
next in thread | previous in thread | raw e-mail | index | archive | help
> > > > Perhaps we could introduce a new word in the kernel config file. > > > > Something like > > > > cache <n> > > > > where <n> is the amount of L2 cache. The L1 cache is processor specific > > > > and thus can be obtained via the cpu directive. The rest can then be > > > > doen with macros. > > > > > > > Actually, the L1 cache will be changing on P5 class machines soon. > > > > hmm. But that would be identifiable by the stepping number, right? > In the longer term (probably in release timeframe) an attempt to probe > the system interface chips would be useful, upon failure, perhaps > default to 256K. (Most reasonably high perf systems since the > 386 and certainly the 486 have 256K (maybe some 128K) cache.) It > is only the medium 386s that had 64K anyway. ... and Cx486-DLC Also some systems might be supplied without L2 cache altogether, or the cache misconfigured so it is equivalent to non-existence. Is there no reliable probe for cache size that could be coaxed to work on all systems? == Adam
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?199610072322.XAA06650>