Date: Fri, 09 Jan 1998 14:34:44 +0100 From: sthaug@nethelp.no To: grog@lemis.com Cc: hardware@freebsd.org Subject: Re: LS-120, Riva 128, ASUS motherboard Message-ID: <27003.884352884@verdi.nethelp.no> In-Reply-To: Your message of "Fri, 9 Jan 1998 19:40:06 %2B1030" References: <19980109194006.42229@lemis.com>
next in thread | previous in thread | raw e-mail | index | archive | help
> Ahh. http://www.intel.com/design/pcisets/datashts/290559.htm. > Extract: > > The Intel 430TX PCIset (430TX) consists of the 82439TX System > Controller (MTXC) and the 82371AB PCI ISA IDE Xcelerator > (PIIX4). [...] The MTXC integrates the cache and main memory DRAM > control functions and provides bus control to transfers between the > CPU, cache, main memory, and the PCI Bus. The second level (L2) > cache controller supports a writeback cache policy for cache sizes > of 256 Kbytes and 512 Kbytes. > > I'm downloading the document, and will print it out, but this > certainly doesn't sound like Tom's Hardware Guide. I have something called "Intel 430TX PCIset: 82439TX System Controller". It states very clearly on the first page: "64 MB DRAM Cacheability"/ Steinar Haug, Nethelp consulting, sthaug@nethelp.no
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?27003.884352884>