Date: Fri, 15 Dec 1995 15:47:51 -0700 (MST) From: Terry Lambert <terry@lambert.org> To: leisner@sdsp.mc.xerox.com (Marty Leisner) Cc: gurney_j@efn.org, msmith@atrad.adelaide.edu.au, d_burr@ix.netcom.com, alan@trickler.uu.silcom.com, questions@freebsd.org Subject: Re: Upgrade - CPU, clock? Message-ID: <199512152247.PAA04989@phaeton.artisoft.com> In-Reply-To: <9512151531.AA08003@gnu.mc.xerox.com> from "Marty Leisner" at Dec 15, 95 07:31:27 am
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> Can someone comment with some facts on how much difference L2 cache > makes on DX4/100s? DX DX2 (doubled) DX4 (tripled) L1 1 clock 1 clock 1 clock L2 1 cycle 2 cycles 3 cycles Memory 1 + I/O wait 2 + I/O wait 3 + I/O wait A cycle is a memory bus cycle, which may be several clocks, depending on interleaving, burst, etc. Clearly, the higher the clock multiplier, the less use the L2 cache and the more valuable the L1 cache. I have a DX/50 that handily outperforms a DX2/66, all other things being equal, because the L2 cache is accessed at 50 MHz instead of 33MHz, for instance. Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.
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