Date: Thu, 11 Mar 2004 19:06:28 -0800 (PST) From: Juli Mallett <jmallett@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 48750 for review Message-ID: <200403120306.i2C36Si5019445@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=48750 Change 48750 by jmallett@jmallett_oingo on 2004/03/11 19:05:55 Don't do the cute and'ing of bits thing, I don't think I really had a reason. Let alone a good one. Affected files ... .. //depot/projects/mips/sys/mips/mips/locore.S#10 edit Differences ... ==== //depot/projects/mips/sys/mips/mips/locore.S#10 (text+ko) ==== @@ -50,31 +50,23 @@ .set noreorder .text - .globl btext -btext: +GLOBAL(btext) ENTRY(start) /* - * t0: Bits to preserve if set: - * Soft reset - * Boot exception vectors (firmware-provided) - */ - li t0, MIPS_SR_BEV | MIPS_SR_SR - /* - * t1: Bits to set explicitly: + * t0: Bits to set: * Kernel mode is 64-bit * Enable FPU */ - li t1, MIPS_SR_KX | MIPS_SR_COP_1_BIT + li t0, MIPS_SR_KX | MIPS_SR_COP_1_BIT /* * Read coprocessor 0 status register, clear bits not * preserved (namely, clearing interrupt bits), and set * bits we want to explicitly set. */ - mfc0 t2, MIPS_COP_0_STATUS - and t2, t0 - or t2, t1 - mtc0 t2, MIPS_COP_0_STATUS + mfc0 t1, MIPS_COP_0_STATUS + or t1, t0 + mtc0 t1, MIPS_COP_0_STATUS COP0_SYNC /* Extra nops for the FPU to spin up. */
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