Date: Tue, 3 Dec 2019 10:13:45 +0100 From: Emmanuel Vadot <manu@bidouilliste.com> To: Ravi Pokala <rpokala@freebsd.org> Cc: Emmanuel Vadot <manu@FreeBSD.org>, <src-committers@freebsd.org>, <svn-src-all@freebsd.org>, <svn-src-head@freebsd.org> Subject: Re: svn commit: r355188 - in head/riscv: . sifive Message-ID: <20191203101345.53896cce499ee685000e661a@bidouilliste.com> In-Reply-To: <3C503BF7-6D49-4FD2-B2C4-55C890FA8458@panasas.com> References: <201911281938.xASJcv3a034087@repo.freebsd.org> <3C503BF7-6D49-4FD2-B2C4-55C890FA8458@panasas.com>
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On Mon, 02 Dec 2019 13:36:06 -0800
Ravi Pokala <rpokala@freebsd.org> wrote:
> Hi Manu,
>=20
> This creates a top-level "riscv" directory, but there are no other top-le=
vel ${TARGET} directories.
>=20
> It looks like other *.dts and *.dtsi files live in either
>=20
> sys/dts/${TARGET}
>=20
> or
>=20
> sys/gnu/dts/${TARGET}/(vendor/)?
>=20
> So perhaps these should be moved to one of those directories, as appropri=
ate?
>=20
> Thanks,
>=20
> Ravi (rpokala@)
Thanks, I don't know how I didn't see that ... fixed with revert +
r355324.
> ?-----Original Message-----
> From: <owner-src-committers@freebsd.org> on behalf of Emmanuel Vadot <man=
u@FreeBSD.org>
> Date: 2019-11-28, Thursday at 11:38
> To: <src-committers@freebsd.org>, <svn-src-all@freebsd.org>, <svn-src-hea=
d@freebsd.org>
> Subject: svn commit: r355188 - in head/riscv: . sifive
>=20
> Author: manu
> Date: Thu Nov 28 19:38:57 2019
> New Revision: 355188
> URL: https://svnweb.freebsd.org/changeset/base/355188
> =20
> Log:
> Import riscv DTS files
> =20
> Requested by: mhorne
> =20
> Added:
> head/riscv/
> - copied from r355184, vendor/device-tree/dist/src/riscv/
> Replaced:
> head/riscv/sifive/fu540-c000.dtsi
> - copied unchanged from r355185, vendor/device-tree/dist/src/ris=
cv/sifive/fu540-c000.dtsi
> head/riscv/sifive/hifive-unleashed-a00.dts
> - copied unchanged from r355185, vendor/device-tree/dist/src/ris=
cv/sifive/hifive-unleashed-a00.dts
> =20
> Copied: head/riscv/sifive/fu540-c000.dtsi (from r355185, vendor/devic=
e-tree/dist/src/riscv/sifive/fu540-c000.dtsi)
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D
> --- /dev/null 00:00:00 1970 (empty, because file is newly added)
> +++ head/riscv/sifive/fu540-c000.dtsi Thu Nov 28 19:38:57 2019 (r3551=
88, copy of r355185, vendor/device-tree/dist/src/riscv/sifive/fu540-c000.dt=
si)
> @@ -0,0 +1,251 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2018-2019 SiFive, Inc */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/clock/sifive-fu540-prci.h>
> +
> +/ {
> + #address-cells =3D <2>;
> + #size-cells =3D <2>;
> + compatible =3D "sifive,fu540-c000", "sifive,fu540";
> +
> + aliases {
> + serial0 =3D &uart0;
> + serial1 =3D &uart1;
> + ethernet0 =3D ð0;
> + };
> +
> + chosen {
> + };
> +
> + cpus {
> + #address-cells =3D <1>;
> + #size-cells =3D <0>;
> + cpu0: cpu@0 {
> + compatible =3D "sifive,e51", "sifive,rocket0", "riscv";
> + device_type =3D "cpu";
> + i-cache-block-size =3D <64>;
> + i-cache-sets =3D <128>;
> + i-cache-size =3D <16384>;
> + reg =3D <0>;
> + riscv,isa =3D "rv64imac";
> + status =3D "disabled";
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells =3D <1>;
> + compatible =3D "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu1: cpu@1 {
> + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv";
> + d-cache-block-size =3D <64>;
> + d-cache-sets =3D <64>;
> + d-cache-size =3D <32768>;
> + d-tlb-sets =3D <1>;
> + d-tlb-size =3D <32>;
> + device_type =3D "cpu";
> + i-cache-block-size =3D <64>;
> + i-cache-sets =3D <64>;
> + i-cache-size =3D <32768>;
> + i-tlb-sets =3D <1>;
> + i-tlb-size =3D <32>;
> + mmu-type =3D "riscv,sv39";
> + reg =3D <1>;
> + riscv,isa =3D "rv64imafdc";
> + tlb-split;
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells =3D <1>;
> + compatible =3D "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu2: cpu@2 {
> + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv";
> + d-cache-block-size =3D <64>;
> + d-cache-sets =3D <64>;
> + d-cache-size =3D <32768>;
> + d-tlb-sets =3D <1>;
> + d-tlb-size =3D <32>;
> + device_type =3D "cpu";
> + i-cache-block-size =3D <64>;
> + i-cache-sets =3D <64>;
> + i-cache-size =3D <32768>;
> + i-tlb-sets =3D <1>;
> + i-tlb-size =3D <32>;
> + mmu-type =3D "riscv,sv39";
> + reg =3D <2>;
> + riscv,isa =3D "rv64imafdc";
> + tlb-split;
> + cpu2_intc: interrupt-controller {
> + #interrupt-cells =3D <1>;
> + compatible =3D "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu3: cpu@3 {
> + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv";
> + d-cache-block-size =3D <64>;
> + d-cache-sets =3D <64>;
> + d-cache-size =3D <32768>;
> + d-tlb-sets =3D <1>;
> + d-tlb-size =3D <32>;
> + device_type =3D "cpu";
> + i-cache-block-size =3D <64>;
> + i-cache-sets =3D <64>;
> + i-cache-size =3D <32768>;
> + i-tlb-sets =3D <1>;
> + i-tlb-size =3D <32>;
> + mmu-type =3D "riscv,sv39";
> + reg =3D <3>;
> + riscv,isa =3D "rv64imafdc";
> + tlb-split;
> + cpu3_intc: interrupt-controller {
> + #interrupt-cells =3D <1>;
> + compatible =3D "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu4: cpu@4 {
> + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv";
> + d-cache-block-size =3D <64>;
> + d-cache-sets =3D <64>;
> + d-cache-size =3D <32768>;
> + d-tlb-sets =3D <1>;
> + d-tlb-size =3D <32>;
> + device_type =3D "cpu";
> + i-cache-block-size =3D <64>;
> + i-cache-sets =3D <64>;
> + i-cache-size =3D <32768>;
> + i-tlb-sets =3D <1>;
> + i-tlb-size =3D <32>;
> + mmu-type =3D "riscv,sv39";
> + reg =3D <4>;
> + riscv,isa =3D "rv64imafdc";
> + tlb-split;
> + cpu4_intc: interrupt-controller {
> + #interrupt-cells =3D <1>;
> + compatible =3D "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> + soc {
> + #address-cells =3D <2>;
> + #size-cells =3D <2>;
> + compatible =3D "sifive,fu540-c000", "sifive,fu540", "simple-bus";
> + ranges;
> + plic0: interrupt-controller@c000000 {
> + #interrupt-cells =3D <1>;
> + compatible =3D "sifive,plic-1.0.0";
> + reg =3D <0x0 0xc000000 0x0 0x4000000>;
> + riscv,ndev =3D <53>;
> + interrupt-controller;
> + interrupts-extended =3D <
> + &cpu0_intc 0xffffffff
> + &cpu1_intc 0xffffffff &cpu1_intc 9
> + &cpu2_intc 0xffffffff &cpu2_intc 9
> + &cpu3_intc 0xffffffff &cpu3_intc 9
> + &cpu4_intc 0xffffffff &cpu4_intc 9>;
> + };
> + prci: clock-controller@10000000 {
> + compatible =3D "sifive,fu540-c000-prci";
> + reg =3D <0x0 0x10000000 0x0 0x1000>;
> + clocks =3D <&hfclk>, <&rtcclk>;
> + #clock-cells =3D <1>;
> + };
> + uart0: serial@10010000 {
> + compatible =3D "sifive,fu540-c000-uart", "sifive,uart0";
> + reg =3D <0x0 0x10010000 0x0 0x1000>;
> + interrupt-parent =3D <&plic0>;
> + interrupts =3D <4>;
> + clocks =3D <&prci PRCI_CLK_TLCLK>;
> + status =3D "disabled";
> + };
> + uart1: serial@10011000 {
> + compatible =3D "sifive,fu540-c000-uart", "sifive,uart0";
> + reg =3D <0x0 0x10011000 0x0 0x1000>;
> + interrupt-parent =3D <&plic0>;
> + interrupts =3D <5>;
> + clocks =3D <&prci PRCI_CLK_TLCLK>;
> + status =3D "disabled";
> + };
> + i2c0: i2c@10030000 {
> + compatible =3D "sifive,fu540-c000-i2c", "sifive,i2c0";
> + reg =3D <0x0 0x10030000 0x0 0x1000>;
> + interrupt-parent =3D <&plic0>;
> + interrupts =3D <50>;
> + clocks =3D <&prci PRCI_CLK_TLCLK>;
> + reg-shift =3D <2>;
> + reg-io-width =3D <1>;
> + #address-cells =3D <1>;
> + #size-cells =3D <0>;
> + status =3D "disabled";
> + };
> + qspi0: spi@10040000 {
> + compatible =3D "sifive,fu540-c000-spi", "sifive,spi0";
> + reg =3D <0x0 0x10040000 0x0 0x1000
> + 0x0 0x20000000 0x0 0x10000000>;
> + interrupt-parent =3D <&plic0>;
> + interrupts =3D <51>;
> + clocks =3D <&prci PRCI_CLK_TLCLK>;
> + #address-cells =3D <1>;
> + #size-cells =3D <0>;
> + status =3D "disabled";
> + };
> + qspi1: spi@10041000 {
> + compatible =3D "sifive,fu540-c000-spi", "sifive,spi0";
> + reg =3D <0x0 0x10041000 0x0 0x1000
> + 0x0 0x30000000 0x0 0x10000000>;
> + interrupt-parent =3D <&plic0>;
> + interrupts =3D <52>;
> + clocks =3D <&prci PRCI_CLK_TLCLK>;
> + #address-cells =3D <1>;
> + #size-cells =3D <0>;
> + status =3D "disabled";
> + };
> + qspi2: spi@10050000 {
> + compatible =3D "sifive,fu540-c000-spi", "sifive,spi0";
> + reg =3D <0x0 0x10050000 0x0 0x1000>;
> + interrupt-parent =3D <&plic0>;
> + interrupts =3D <6>;
> + clocks =3D <&prci PRCI_CLK_TLCLK>;
> + #address-cells =3D <1>;
> + #size-cells =3D <0>;
> + status =3D "disabled";
> + };
> + eth0: ethernet@10090000 {
> + compatible =3D "sifive,fu540-c000-gem";
> + interrupt-parent =3D <&plic0>;
> + interrupts =3D <53>;
> + reg =3D <0x0 0x10090000 0x0 0x2000
> + 0x0 0x100a0000 0x0 0x1000>;
> + local-mac-address =3D [00 00 00 00 00 00];
> + clock-names =3D "pclk", "hclk";
> + clocks =3D <&prci PRCI_CLK_GEMGXLPLL>,
> + <&prci PRCI_CLK_GEMGXLPLL>;
> + #address-cells =3D <1>;
> + #size-cells =3D <0>;
> + status =3D "disabled";
> + };
> + pwm0: pwm@10020000 {
> + compatible =3D "sifive,fu540-c000-pwm", "sifive,pwm0";
> + reg =3D <0x0 0x10020000 0x0 0x1000>;
> + interrupt-parent =3D <&plic0>;
> + interrupts =3D <42 43 44 45>;
> + clocks =3D <&prci PRCI_CLK_TLCLK>;
> + #pwm-cells =3D <3>;
> + status =3D "disabled";
> + };
> + pwm1: pwm@10021000 {
> + compatible =3D "sifive,fu540-c000-pwm", "sifive,pwm0";
> + reg =3D <0x0 0x10021000 0x0 0x1000>;
> + interrupt-parent =3D <&plic0>;
> + interrupts =3D <46 47 48 49>;
> + clocks =3D <&prci PRCI_CLK_TLCLK>;
> + #pwm-cells =3D <3>;
> + status =3D "disabled";
> + };
> +
> + };
> +};
> =20
> Copied: head/riscv/sifive/hifive-unleashed-a00.dts (from r355185, ven=
dor/device-tree/dist/src/riscv/sifive/hifive-unleashed-a00.dts)
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D
> --- /dev/null 00:00:00 1970 (empty, because file is newly added)
> +++ head/riscv/sifive/hifive-unleashed-a00.dts Thu Nov 28 19:38:57 20=
19 (r355188, copy of r355185, vendor/device-tree/dist/src/riscv/sifive/hifi=
ve-unleashed-a00.dts)
> @@ -0,0 +1,96 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2018-2019 SiFive, Inc */
> +
> +#include "fu540-c000.dtsi"
> +
> +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
> +#define RTCCLK_FREQ 1000000
> +
> +/ {
> + #address-cells =3D <2>;
> + #size-cells =3D <2>;
> + model =3D "SiFive HiFive Unleashed A00";
> + compatible =3D "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
> +
> + chosen {
> + stdout-path =3D "serial0";
> + };
> +
> + cpus {
> + timebase-frequency =3D <RTCCLK_FREQ>;
> + };
> +
> + memory@80000000 {
> + device_type =3D "memory";
> + reg =3D <0x0 0x80000000 0x2 0x00000000>;
> + };
> +
> + soc {
> + };
> +
> + hfclk: hfclk {
> + #clock-cells =3D <0>;
> + compatible =3D "fixed-clock";
> + clock-frequency =3D <33333333>;
> + clock-output-names =3D "hfclk";
> + };
> +
> + rtcclk: rtcclk {
> + #clock-cells =3D <0>;
> + compatible =3D "fixed-clock";
> + clock-frequency =3D <RTCCLK_FREQ>;
> + clock-output-names =3D "rtcclk";
> + };
> +};
> +
> +&uart0 {
> + status =3D "okay";
> +};
> +
> +&uart1 {
> + status =3D "okay";
> +};
> +
> +&i2c0 {
> + status =3D "okay";
> +};
> +
> +&qspi0 {
> + status =3D "okay";
> + flash@0 {
> + compatible =3D "issi,is25wp256", "jedec,spi-nor";
> + reg =3D <0>;
> + spi-max-frequency =3D <50000000>;
> + m25p,fast-read;
> + spi-tx-bus-width =3D <4>;
> + spi-rx-bus-width =3D <4>;
> + };
> +};
> +
> +&qspi2 {
> + status =3D "okay";
> + mmc@0 {
> + compatible =3D "mmc-spi-slot";
> + reg =3D <0>;
> + spi-max-frequency =3D <20000000>;
> + voltage-ranges =3D <3300 3300>;
> + disable-wp;
> + };
> +};
> +
> +ð0 {
> + status =3D "okay";
> + phy-mode =3D "gmii";
> + phy-handle =3D <&phy0>;
> + phy0: ethernet-phy@0 {
> + reg =3D <0>;
> + };
> +};
> +
> +&pwm0 {
> + status =3D "okay";
> +};
> +
> +&pwm1 {
> + status =3D "okay";
> +};
> =20
--=20
Emmanuel Vadot <manu@bidouilliste.com> <manu@freebsd.org>
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