Date: Wed, 15 Feb 2017 13:45:10 -0800 From: Mark Millard <markmi@dsl-only.net> To: Oliver Pinter <oliver.pinter@hardenedbsd.org> Cc: Andrew Turner <andrew@fubar.geek.nz>, svn-src-head@freebsd.org Subject: Re: svn commit: r313772 - head/sys/arm64/arm64 Message-ID: <22EF24E0-3DEA-44C4-AE23-2290082CB574@dsl-only.net> In-Reply-To: <CAPQ4ffvNczu9g3QLMKgbdYw-LDJXQiyafQSqSjC5AFRNH36RoQ@mail.gmail.com> References: <62A5F129-EFD3-496B-854C-9D8623EFFD38@dsl-only.net> <CAPQ4ffvNczu9g3QLMKgbdYw-LDJXQiyafQSqSjC5AFRNH36RoQ@mail.gmail.com>
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On 2017-Feb-15, at 1:39 PM, Oliver Pinter = <oliver.pinter@hardenedbsd.org> wrote: > On 2/15/17, Mark Millard <markmi@dsl-only.net> wrote: >>> Author: andrew >>> Date: Wed Feb 15 14:56:47 2017 >>> New Revision: 313772 >>> URL: >>> https://svnweb.freebsd.org/changeset/base/313772 >>>=20 >>> Log: >>> Load the new sp_el0 with interrupts disabled in fork_trampoline. If = an >>> interrupt arrives in fork_trampoline after sp_el0 was written we = may >>> then >>> switch to a new thread, enter userland so change this stack = pointer, >>> then >>> return to this code with the wrong value. This fixes this case by >>> moving >>> the load of sp_el0 until after interrupts have been disabled. >>=20 >> = https://svnweb.freebsd.org/base/stable/11/sys/arm64/arm64/swtch.S?revision= =3D302408&view=3Dmarkup >>=20 >> shows stable/11 has the same issue. >>=20 >> Is this to be MFC'd at some point? >>=20 >>=20 >> stable/10 seems to have a different code structure: >>=20 >> https://svnweb.freebsd.org/base/stable/10/sys/amd64/amd64/ >=20 > This is x86-64 aka amd64 in FreeBSD, in 10-STABLE only 32 bit ARM > support exists, so there isn't arm64. Clearly I was somewhat distracted and careless when I looked at stable/10. Sorry for the noise in that part. Still the stable/11 part does apply: at least I got something right. >>=20 >> . . . =3D=3D=3D Mark Millard markmi at dsl-only.net
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