Date: Thu, 8 Jan 2009 16:30:29 GMT From: Nathan Whitehorn <nwhitehorn@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 155823 for review Message-ID: <200901081630.n08GUTeT038483@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=155823 Change 155823 by nwhitehorn@nwhitehorn_trantor on 2009/01/08 16:30:00 970 CPUs don't implement the L2 and L3 cache configuration registers, so we should not try to program them. We should have a better scheme (a CPU features mask) for controlling this -- right now we just check if the stored values for the L2CR and L3CR are zero. This commit makes SMP work in the simulator, modulo platform-specific issues starting the CPU. It may work on real (Apple) hardware. The CPU start/stop bits of this file should be abstracted into a platform module. Affected files ... .. //depot/projects/ppc-g5/sys/powerpc/aim/mp_cpudep.c#3 edit Differences ... ==== //depot/projects/ppc-g5/sys/powerpc/aim/mp_cpudep.c#3 (text+ko) ==== @@ -250,8 +250,10 @@ mtmsr(msr); isync(); - reg = l3_enable(); - reg = l2_enable(); + if (l3cr_config != 0) + reg = l3_enable(); + if (l2cr_config != 0) + reg = l2_enable(); reg = l1d_enable(); reg = l1i_enable();
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