Date: Tue, 10 Sep 2013 10:13:31 -0600 From: Warner Losh <imp@bsdimp.com> To: John-Mark Gurney <jmg@funkthat.com> Cc: freebsd-arm@freebsd.org Subject: Re: Architecture vs. bus vs. device DMA cache coherency Message-ID: <B6ECC3B2-E400-4F2D-9514-C757D7C850AC@bsdimp.com> In-Reply-To: <20130910154335.GT68682@funkthat.com> References: <CAFHCsPXe97B3YKURXZUqiNtWzopJZ2e00qaOBBU16nQYMM1pdg@mail.gmail.com> <20130910154335.GT68682@funkthat.com>
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On Sep 10, 2013, at 9:43 AM, John-Mark Gurney wrote: > Svatopluk Kraus wrote this message on Tue, Sep 10, 2013 at 13:19 = +0200: >> Even in DMA cache coherent architectures there could be not-coherent = DMA >> busses and/or devices. Thus, each bus and/or device should be = described by >> its bus_dma_tag and the tag should carry information about DMA cache >> coherency. >=20 > I've thought about this a lot myself, and I'm not familar w/ a bus = (that > isn't main memory) or device that isn't cache coherent... Most busses > write to memory through an arbiter (north bridge or cpu/soc) that does > the proper read/modify/write cycles to get the memory there. I have > not heard of another bus/device that does their own read/modify/write > cycles to get their writes to memory. Can you name a current = bus/device > that does this? >=20 > Our busdma system does have issues that if you try to dma to say, > video memory, we don't handle that (well) because we assume that all > memory is a flat space and belongs to nexus, but this isn't always > correct. >=20 > If you have an architecture like this, can you please tell use which > system you are trying to fix? I know that MIPS has different kinds of coherency as well that we = generally map to coherent (meaning coherent enough for the users) or = incoherent. Something to keep in mind. I generally like the idea, but don't have enough experience with kind of = hardware to know if the design is a good one. Warner
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