Date: Mon, 22 Nov 2010 09:20:15 -0500 From: John Baldwin <jhb@freebsd.org> To: freebsd-hackers@freebsd.org Cc: Sergio =?iso-8859-1?q?Andr=E9s_G=F3mez_del_Real?= <sergio.g.delreal@gmail.com> Subject: Re: Quick i386 question... Message-ID: <201011220920.15431.jhb@freebsd.org> In-Reply-To: <AANLkTikjX28eu3_Zv0XFcE1LG-7UNVv9DupHCZ9T0qiv@mail.gmail.com> References: <AANLkTikjX28eu3_Zv0XFcE1LG-7UNVv9DupHCZ9T0qiv@mail.gmail.com>
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On Saturday, November 20, 2010 3:38:58 pm Sergio Andr=E9s G=F3mez del Real = wrote: > If received an interrupt while in protected-mode and paging enabled, > is linear address from IDT stored at the idtr translated using the > paging-hierarchy structures? > I have looked at the interrupt/exception chapter in the corresponding > Intel manual but can't find the answer. Maybe I overlooked. Yes. A linear address is the flat virtual address after segments are taken= =20 into account. It is the address used as an input to the paging support in = the=20 MMU. =2D-=20 John Baldwin
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