Date: Fri, 14 Sep 2007 23:50:06 GMT From: dfilter@FreeBSD.ORG (dfilter service) To: freebsd-bugs@FreeBSD.org Subject: Re: kern/103841: commit references a PR Message-ID: <200709142350.l8ENo6CJ023783@freefall.freebsd.org>
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The following reply was made to PR kern/103841; it has been noted by GNATS.
From: dfilter@FreeBSD.ORG (dfilter service)
To: bug-followup@FreeBSD.org
Cc:
Subject: Re: kern/103841: commit references a PR
Date: Fri, 14 Sep 2007 23:44:17 +0000 (UTC)
jkim 2007-09-14 23:44:11 UTC
FreeBSD src repository
Modified files: (Branch: RELENG_6)
sys/dev/fdc fdc.c
sys/dev/ic nec765.h
sys/pc98/cbus fdc.c
Log:
MFC: sys/dev/fdc/fdc.c 1.310-1.313
sys/dev/ic/nec765.h 1.12, 1.13
sys/dev/pc98/fdc.c 1.167
- Enhanced floppy controllers have Data Rate Select Register (DSR) at 0x3f4.
Use it to reset controller and to select data rate. According to Intel
80277AA datasheet, software reset behaves the same as DOR reset except
that it is self clearing. National Semiconductor PC8477B datasheet says
the same. As a side effect, we no longer use Configuration Control
Register (CCR) at 0x3f7 for these controllers, which is often missing
in modern hardware.
- Assume floppy disk is not inserted when we have exhausted retries. This
significantly reduces booting time when there is broken floppy disk drive,
controller, cable, BIOS, etc.
When the floppy controller interface is correctly implemented, disk change
signal (DSKCHG) is reflected in the Digital Input Register (DIR) at 0x3f7.
However, there are many cases that the signal is unusable. Moreover, some
BIOS does not reserve the port at all. In those cases, the register may not
function.
- Fix style nits.
PR: kern/103841
Revision Changes Path
1.307.2.4 +27 -8 src/sys/dev/fdc/fdc.c
1.11.8.1 +29 -23 src/sys/dev/ic/nec765.h
1.160.2.4 +2 -2 src/sys/pc98/cbus/fdc.c
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