Date: Fri, 28 Dec 2012 12:20:38 +0400 From: Gleb Smirnoff <glebius@FreeBSD.org> To: Attilio Rao <attilio@FreeBSD.org> Cc: svn-src-head@FreeBSD.org, svn-src-all@FreeBSD.org, src-committers@FreeBSD.org Subject: Re: svn commit: r244732 - head/sys/sys Message-ID: <20121228082038.GZ80310@FreeBSD.org> In-Reply-To: <CAJ-FndDeE15ygFKm1=euyvE8PW=HyUiK7WUcfgpX04Nj4GuExA@mail.gmail.com> References: <201212271236.qBRCawuU078203@svn.freebsd.org> <20121227124657.GX80310@FreeBSD.org> <CAJ-FndD9aDfPprwBYC%2B3T1WsfE1b4aZJENRAjo%2BhFEL1NLBKmw@mail.gmail.com> <20121227132507.GY80310@FreeBSD.org> <CAJ-FndC6Xq4EWcU203E4ucgr=jzOAutBBBkn%2BO1Qs0nL0i_Q3A@mail.gmail.com> <CAJ-FndAzqHCNtLGFH=6Cm3rshMestSZz_naF1=saMEKuX9cyog@mail.gmail.com> <CAJ-FndDeE15ygFKm1=euyvE8PW=HyUiK7WUcfgpX04Nj4GuExA@mail.gmail.com>
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On Thu, Dec 27, 2012 at 08:37:24AM -0800, Attilio Rao wrote: A> > Speaking of which, as you are here, I just found out that r241037 A> > breaks the alignment of the structure. A> > Infact the padding member is not updated accordingly. A> > A> > We don't have a param to control L2 caches, but I think that we can A> > safely align them to the L1 cacheline for sure. A> > Also, note that this padding is completely broken for MI requirements A> > (it just assumes blindly 128 bytes L2 cachelines, which not always A> > true even on i386). A> A> More specifically this patch: A> http://www.freebsd.org/~attilio/bufring_pad.patch A> A> Of course I don't think the optimization is important in the A> DEBUG_BUFRING on case, so the patch should be fine. Agreed, thanks. And thanks for removing the br_prod_bufs. Sorry for breaking alignment in r241037. And last time we talked about alignment, it was noticed that our current CACHE_LINE_SIZE on amd64 is 128, while real size is 64. This 128 was some optimisation proposed by Intel for some past generation of CPUs and is no longer actual. Shouldn't we change it back to 64? -- Totus tuus, Glebius.
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