Date: Tue, 6 Jul 2010 15:31:58 +0000 (UTC) From: Nathan Whitehorn <nwhitehorn@FreeBSD.org> To: cvs-src-old@freebsd.org Subject: cvs commit: src/sys/powerpc/powerpc openpic.c Message-ID: <201007061532.o66FW89f020911@repoman.freebsd.org>
next in thread | raw e-mail | index | archive | help
nwhitehorn 2010-07-06 15:31:58 UTC
FreeBSD src repository
Modified files:
sys/powerpc/powerpc openpic.c
Log:
SVN rev 209725 on 2010-07-06 15:31:58Z by nwhitehorn
Fix interrupt distribution to multiple CPUs on systems with cascaded PICs.
Because slave PICs send all interrupts to their CPU 0 output line (which
is routed to a pin on the master PIC), changes to per-CPU register banks
like EOI on the slave PIC must be accessed for CPU 0, instead of the
CPU actually processing the interrupt.
Submitted by: Andreas Tobler
Revision Changes Path
1.30 +14 -7 src/sys/powerpc/powerpc/openpic.c
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201007061532.o66FW89f020911>