Date: Thu, 14 May 2009 23:35:36 -0600 (MDT) From: "M. Warner Losh" <imp@bsdimp.com> To: stas@FreeBSD.org Cc: svn-src-head@FreeBSD.org, svn-src-all@FreeBSD.org, src-committers@FreeBSD.org Subject: Re: svn commit: r192027 - head/sys/arm/at91 Message-ID: <20090514.233536.1299798630.imp@bsdimp.com> In-Reply-To: <20090515092205.6f6d06fa.stas@FreeBSD.org> References: <200905122114.n4CLEag9033208@svn.freebsd.org> <20090514.213712.-404854369.imp@bsdimp.com> <20090515092205.6f6d06fa.stas@FreeBSD.org>
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In message: <20090515092205.6f6d06fa.stas@FreeBSD.org>
Stanislav Sedov <stas@FreeBSD.org> writes:
: On Thu, 14 May 2009 21:37:12 -0600 (MDT)
: "M. Warner Losh" <imp@bsdimp.com> mentioned:
:
: > In message: <200905122114.n4CLEag9033208@svn.freebsd.org>
: > Stanislav Sedov <stas@FreeBSD.org> writes:
: > : @@ -926,6 +937,7 @@ atestart_locked(struct ifnet *ifp)
: > : * tell the hardware to xmit the packet.
: > : */
: > : WR4(sc, ETH_TAR, segs[0].ds_addr);
: > : + BARRIER(sc, ETH_TAR, 8, BUS_SPACE_BARRIER_WRITE);
: > : WR4(sc, ETH_TCR, segs[0].ds_len);
: >
: > Why is a barrier needed here?
: >
: Writing the TCR register triggers the transmit, so it had to be written
: strongly after the TAR register. That's why I added the barrier here.
Then shouldn't the barrier be after TCR write? Or does this ensure
that the write is before TCR?
Warner
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