Date: Sat, 12 Jan 2002 17:36:43 +1100 (EST) From: Bruce Evans <bde@zeta.org.au> To: Peter Wemm <peter@wemm.org> Cc: Mark Murray <mark@grondar.za>, Chris Faulhaber <jedgar@fxp.org>, <scottl@FreeBSD.ORG>, <smp@FreeBSD.ORG> Subject: Re: P5 vs. SMP, part 2 Message-ID: <20020112173153.G4872-100000@gamplex.bde.org> In-Reply-To: <20020112034904.7784A38FD@overcee.netplex.com.au>
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On Fri, 11 Jan 2002, Peter Wemm wrote: > The problem is that the AP cpus were running with the CR0_CD (cache disable) > and CR0_NW (cache writethrough, not writeback). This is very bad. :-] > > PPro and above bioses seem to cause the AP cpus enter the kernel with cache > enabled, so that this looks like it should be a p5/i586 problem only. Where were they set before? initcpu() has a mazing amount of code for setting these bits. We should set all CR* bits that we know and care about. We also sort of depend on BIOSes to clear CR4_TSD so that the TSC works in user mode. The TSC in user mode is not really supported, but I often use it. Bruce To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-smp" in the body of the message
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