Date: Mon, 22 May 2006 12:55:43 -0600 From: "Chad Leigh -- Shire.Net LLC" <chad@shire.net> To: Eric Anderson <anderson@centtech.com> Cc: current@freebsd.org, m m <needacoder@gmail.com> Subject: Re: FreeBSD is now self-hosting on the UltraSPARC T1 Message-ID: <F47557C7-388A-4577-A365-5F22AF4A049D@shire.net> In-Reply-To: <4471E7FB.3090400@centtech.com> References: <1e4841eb0605211854i44c4aa4cm9dfc72506c2232ea@mail.gmail.com> <FB03D201-4154-411E-AFE4-572CEBF76A92@shire.net> <4471E7FB.3090400@centtech.com>
next in thread | previous in thread | raw e-mail | index | archive | help
On May 22, 2006, at 10:34 AM, Eric Anderson wrote: > Chad Leigh -- Shire.Net LLC wrote: >> On May 21, 2006, at 7:54 PM, m m wrote: >>> While >>> on topic, the Opterons aren't SMP either, and neither are the >>> ht-Xeons... >> I would like t\o hear the rational for the Opterons (presumably >> the dual core ones) not being SMP. They have two independent >> operating cores in one physical package. Who cares how it is >> packaged? I would tend to agree with you on the ht-Xeon in terms >> of general descriptions. I do not know as well how the ht-xeon >> work as I don't use any but it seems to me that the "SMP" moniker, >> at least in FreeBSD, relate to how things are scheduled. >> Btw, Opteron MB with a single dual-core ship get a BIOS report on >> Boot of having 2 CPUs... > > Careful - two cores doesn't mean two caches, and isn't always just > 'two cores glued into one package'. > But on the Opteron, the subject of the discussion, it does. They have two caches. The Intel Core Duo dies not. Chad > ------------------------------------------------------------------- --- Chad Leigh -- Shire.Net LLC Your Web App and Email hosting provider chad at shire.net
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?F47557C7-388A-4577-A365-5F22AF4A049D>